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features ? high fsk sensitivity: ?106 dbm at 20 kb it/s/?109.5 dbm at 2.4 kbit/s (433.92 mhz) high ask sensitivity: ?112.5 dbm at 10 kb it/s/?116.5 dbm at 2.4 kbit/s (433.92 mhz) low supply current: 10.5 ma in rx and tx mode (3v/tx with 5 dbm) data rate 1 to 20 kbit/s manchester fsk, 1 to 10 kbit/s manchester ask ask/fsk receiver uses a low-if architecture with high selectivity, blocking and low intermodulation (typical blocking 55 db at 750 khz/61 db at 1.5 mhz and 70 db at 10 mhz, system i1dbcp = ?30 dbm/system iip3 = ?20 dbm) 226 khz if frequency with 30 db image re jection and 170 khz usable if bandwidth transmitter uses closed loop fractional-n synthesizer for fsk modulation with a high pll bandwidth and an excellent isolation between pll and pa tolerances of xtal compensated by fr actional-n synthesizer with 800 hz rf resolution integrated rx/tx-switch, single-ended rf input and output rssi (received signal strength indicator) communication to microcontroller with spi interface working at maximum 500 kbit/s configurable self polling and rx/tx protocol handling with fifo-ram buffering of received and transmitted data 5 push button inputs and one wake-up input are active in power-down mode integrated xtal capacitors pa efficiency: up to 38% (433 mhz/10 dbm/3v) low inband sensitivity change of typically 1.8 db within 58 khz center frequency change in the complete temperature and supply voltage range supply voltage switch, supply voltage regu lator, reset generati on, clock/interrupt generation and low battery indicator for microcontroller fully integrated pll with low ph ase noise vco and pll loop filter sophisticated threshold control and quasi p eak detector circuit in the data slicer power management via different operation modes 433.92 mhz, 868.3 mhz and 315 mhz without external vco and pll components inductive supply with voltage regulator if battery is empty (aux mode) efficient xto start-up circuit (> ?1.5 k ? worst case start impedance) changing of modulation type ask/fsk an d data rate withou t component changes minimal external circuitry requirements for complete system solution adjustable output power: 0 to 10 dbm adjust ed and stabilized with external resistor esd protection at all pins (2 kv hbm, 200 v mm) supply voltage range: 2.4v to 3.6v or 4.4v to 6.6v temperature range: ?40c to +105c small 7 7 mm qfn48 package uhf ask/fsk transceiver ata5811 ata5812 4689f?rke?08/06
2 4689f?rke?08/06 ata5811/ata5812 applications automotive keyless entry and passive entry go systems access control systems remote control systems alarm and telemetry systems energy metering home automation benefits no saw device needed in key fob desi gns to meet automo tive specifications low system cost due to very high system integration level only one crystal needed in system less demanding specification for the microcontroller due to ha ndling of powe r-down mode, delivering of clock, reset, low battery indicat ion and complete handlin g of receive/transmit protocol and polling single-ended design with high isolation of pll/vco from pa and the power supply allows a loop antenna in the key fob to surround the whole application 1. general description the ata5811/ata5812 is a highly integrated uhf ask/fsk single-chann el half-duplex trans- ceiver with low power consumptio n supplied in a small qfn48 package. the receive part is built as a fully integrated low-if receiver, whereas direct pll modulation with the fractional-n synthe- sizer is used for fsk transmission and switch ing of the powe r amplifier for ask transmission. the device supports data rates of 1 kbit/s to 20 kbit/s (fsk) and 1 kbit/s to 10 kbit/s (ask) in manchester, bi-phase and other codes in transparent mode. the ata5811 can be used in the 433 mhz to 435 mhz and the 868 mhz to 870 mhz band, the ata5812 in the 314 mhz to 316 mhz band. the very high system integration level results in few numbers of external compo- nents needed. due to its blocking and selectivity performance, together with the additional 15 db to 20 db loss and the narrow bandwidth of a typical key fob loop antenna, a bulky blocking saw is not needed in the key fob or sensor application. addition ally, the building blocks needed for a typical rke and access control system on both sides, the base and the mobile stations, are fully integrated. its digital control logic with self polling and protocol generation enables a fast challenge response systems without using a high-performance microcontroller. therefore, the ata5811/ata5812 contains a fifo buffer ram and can compose and receive the physical messages themselves. this provides more time for the microcontroller to carry out other func- tions such as calculating crypto algorithms, composing the logical messages and controlling other devices. due to that, a standard 4-/8-bit microcontroller without special periphery and clocked with the clk output of about 4.5 mhz is sufficient to control the communication link. this is especially valid for passive entry and access control systems, where within less than 100 ms several challenge response communications with arbitration of the communication part- ner have to be handled. it is hence possible to design bi-directional rke and access control systems with a fast chal- lenge response crypto function with the same pcb board size and with the same current consumption as uni-directional rke systems.
3 4689f?rke?08/06 ata5811/ata5812 figure 1-1. system block diagram figure 1-2. pinning qfn48 ata5811/ata5812 rf transceiver power supply matching xto 4 to 8 antenna digital control logic microcontroller microcontroller interface rssi cs sck sdi_tmdi sdo_tmdo ata5811/ata5812 clk vsint xtal2 25 nc n_reset irq dem_out nc nc rf_in nc 433_n868 nc rf_out nc pwr_h r_pwr nc nc nc avcc vs2 vs1 vaux test1 dvcc v sout test2 txal1 nc rx_active t1 t2 t3 t4 t5 pwr_on rx_tx1 rx_tx2 cdem 1 2 3 4 9 10 11 5 6 8 7 36 35 34 33 28 27 26 32 31 29 30 nc 12 47 46 45 44 38 37 39 41 40 42 43 14 nc nc 48 13 15 16 17 23 24 22 20 21 19 18
4 4689f?rke?08/06 ata5811/ata5812 table 1-1. pin description pin symbol function 1 nc not connected 2 nc not connected 3 nc not connected 4 rf_in rf input 5 nc not connected 6 433_n868 selects rf input/output frequency range 7 nc not connected 8 r_pwr resistor to adjust output power 9 pwr_h pin to select output power 10 rf_out rf output 11 nc not connected 12 nc not connected 13 nc not connected 14 nc not connected 15 nc not connected 16 avcc blocking of the analog voltage supply 17 vs2 power supply input for voltage range 4.4v to 6.6v 18 vs1 power supply input for voltage range 2.4v to 3.6v 19 vaux auxiliary supply voltage input 20 test1 test input, at gnd during operation 21 dvcc blocking of the digital voltage supply 22 vsout output voltage power supply for external devices 23 test2 test input, at gnd during operation 24 xtal1 reference crystal 25 xtal2 reference crystal 26 nc not connected 27 vsint microcontroller interface supply voltage 28 n_reset output pin to reset a connected microcontroller 29 irq interrupt request 30 clk output to clock a connected microcontroller 31 sdo_tmdo serial data out/transparent mode data out 32 sdi_tmdi serial data in/transparent mode data in 33 sck serial clock 34 dem_out demodulator open drain output signal 35 cs chip select for serial interface 36 rssi output of the rssi amplifier 37 cdem capacitor to adjust the lower cut-off frequency data filter 38 rx_tx2 gnd pin to decouple lna in tx mode 39 rx_tx1 switch pin to decouple lna in tx mode 40 pwr_on input to switch on the system (active high) 41 t5 key input 5 (can also be used to switch on the system (active low)
5 4689f?rke?08/06 ata5811/ata5812 figure 1-3. block diagram 42 t4 key input 4 (can also be used to switch on the system (active low) 43 t3 key input 3 (can also be used to switch on the system (active low) 44 t2 key input 2 (can also be used to switch on the system (active low) 45 t1 key input 1 (can also be used to switch on the system (active low) 46 rx_active indicates rx operation mode 47 nc not connected 48 nc not connected gnd ground/backplane table 1-1. pin description (continued) pin symbol function signal processing (mixer, if filter, if amplifier, demodulator, data filter data slicer) tx/rx - data buffer control register status register polling circuit bit check logic digital control logic power supply switches regulators wakeup reset rf transceiver fractional-n frequency synthesizer vs2 vaux vsout vs1 433_n868 pwr_h cs sdo_tmdo irq n_reset clk dem_out xtal2 xtal1 rssi cdem rf_in rx_tx2 rx_tx1 rf_out r_pwr dvcc rx_active avcc gnd vsint lna spi xto reset pa tx frontend enable pa_enable (ask) demod_out fref freq rx/tx 9 tx_data (fsk) microcontroller interface sck sdi_tmdi t4 t5 tes2 test t1 t3 t2 pwr_on
6 4689f?rke?08/06 ata5811/ata5812 2. typical key fob or sensor application with 1 battery figure 2-1. typical rke key fob or sensor application, 433.92 mhz, 1 battery figure 2-1 shows a typical 433.92 mhz rke key fob or sensor application with one battery the external components are 11 capacitors, 1 resistor, 2 inductors and a crystal. c 1 to c 4 are 68 nf voltage supply blocking capacitors. c 5 is a 10 nf supply blocking capacitor. c 6 is a 15 nf fixed capacitor used for the internal quasi peak detector and for the highpass frequency of the data fil- ter. c 7 to c 11 are rf matching capacitors in the range of 1 pf to 33 pf. l1 is a matching inductor of about 5.6 nh to 56 nh. l 2 is a feed inductor of about 120 nh. a load capacitor of 9 pf for the crystal is integrated. r 1 is typically 22 k ? and sets the output power to about 5.5 dbm. the loop antenna?s quality factor is somewhat reduced by this application due to the quality factor of l 2 and the rx/tx switch. on the other hand, this lower quality factor is necessary to have a robust design with a bandwidth that is broad enough for production tolerances. due to the single-ended and ground-referenced design, the loop antenna can be a free-form wire around the application as it is usually employed in rke uni-directio nal systems. the ata5811/ ata5812 provides suffi- cient isolation and robust pulling behavior of internal circuits from the supply voltage as well as an integrated vco inductor to allow this. since th e efficiency of a loop antenna is proportional to the square of the surrounded area it is beneficial to have a large loop around the application board with a lower quality factor to relax the tolerance specification of the rf components and to get a high antenna efficiency in spite of their lower quality factor. cs nc rssi cdem sck dem_out sdi_tmdi sdo_tmdo ata5811/ata5812 clk vcc vss vsint xtal2 + lithium cell loop antenna avcc 20 mm x 0.4 mm microcontroller 13.25311 mhz n_reset irq nc nc rf_in c 2 c 7 c 11 c 6 c 3 c 1 c 4 433_n868 nc nc nc rf_out pwr_h r_pwr nc avcc vs2 nc nc nc vs1 vaux test1 dvcc vsout test2 txal1 t1 nc nc rx_active t2 t3 t4 t5 pwr_on rx_tx1 rx_tx2 nc c 9 c 10 r 1 l 2 l 1 c 8 c 5
7 4689f?rke?08/06 ata5811/ata5812 3. typical car or sensor base-station application figure 3-1. typical rke car or sensor base-station application, 433.92 mhz figure 3-1 shows a typical 433.92 mhz v cc = 4.75v to 5.25v rke car or sensor base-station application. the external components are 12 capacitors, 1 resistor, 4 inductors, a saw filter and a crystal. c 1 and c 3 to c 4 are 68 nf voltage supply blocking capacitors. c 2 and c 12 are 2.2 f supply blocking capacitors for the internal voltage regulators. c 5 is a 10 nf supply blocking capacitor. c 6 is a 15 nf fixed capacitor used for the internal quasi peak detector and for the highpass frequency of the data filter. c 7 to c 11 are rf matching capacitors in the range of 1 pf to 33 pf. l 2 to l 4 are matching inductors of about 5.6 nh to 56 nh. a load capacitor for the crys- tal of 9 pf is integrated. r 1 is typically 22 k ? and sets the output power at rf_out to about 10 dbm. since a quarter wave or pcb antenna, which has high efficiency and wide band opera- tion, is typically used here, it is recommended to use a saw filter to achieve high sensitivity in case of powerful out-of-band blockers. l 1 , c 10 and c 9 together form a lowpass filter, which is needed to filter out the harmonics in the transmitted signal to meet regulations. an internally reg- ulated voltage at pin vsout can be used in case the microcontroller only supports 3.3v operation, a blocking capacitor with a value of c 12 = 2.2 f has to be connected to vsout in any case. cs nc rssi cdem sck dem_out sdi_tmdi sdo_tmdo ata5811/ata5812 clk vcc vss vsint xtal2 avcc 50 ? connector saw-filter 20 mm x 0.4 mm microcontroller 13.25311 mhz v cc = 4.75v to 5.25v n_reset irq nc nc rf_in c 7 c 11 c 6 c 3 c 2 c 1 c 4 c 12 433_n868 nc nc nc rf_out pwr_h r_pwr nc avcc vs2 nc nc nc vs1 vaux test1 dvcc vsout test2 txal1 t1 nc nc rx_active t2 t3 t4 t5 pwr_on rx_tx1 rx_tx2 nc c 10 c 9 rf out r 1 l 2 l 4 c 8 c 5 l 3 l 1
8 4689f?rke?08/06 ata5811/ata5812 4. typical key fob application, 2 batteries figure 4-1. typical rke key fob application, 433.92 mhz, 2 batteries figure 4-1 shows a typical 433.92 mhz 2-battery rke key fob or sensor application. the exter- nal components are 11 capacitors, 1 resistor, 2 inductors and a crystal. c 1 and c 4 are 68 nf voltage supply blocking capacitors. c 2 and c 3 are 2.2 f supply blocking capacitors for the inter- nal voltage regulators. c 5 is a 10 nf supply blocking capacitor. c 6 is a 15 nf fixed capacitor used for the internal quasi peak detector and for the highpass frequency of the data filter. c 7 to c 11 are rf matching capacitors in the range of 1 pf to 33 pf. l 1 is a matching inductor of about 5.6 nh to 56 nh. l 2 is a feed inductor of about 120 nh. a load capacitor for the crystal of 9 pf is integrated. r 1 is typically 22 k ? and sets the output power to about 5.5 dbm. c 2 c 1 cs nc rssi cdem sck dem_out sdi_tmdi sdo_tmdo ata5811/ata5812 clk vcc vss vsint xtal2 + lithium cells loop antenna avcc 20 mm x 0.4 mm microcontroller 13.25311 mhz n_reset irq nc nc rf_in c 7 c 11 c 6 c 3 c 4 433_n868 nc nc nc rf_out pwr_h r_pwr nc avcc vs2 nc nc nc vs1 vaux test1 dvcc vsout test2 txal1 t1 nc nc rx_active t2 t3 t4 t5 pwr_on rx_tx1 rx_tx2 nc c 9 c 10 r 1 l 2 l 1 c 8 c 5 +
9 4689f?rke?08/06 ata5811/ata5812 5. rf transceiver according to figure 1-3 on page 5 , the rf transceiver consists of an lna (low-noise amplifier), pa (power amplifier), rx/tx switch, fractional-n frequency synthesizer and the signal process- ing part with mixer, if filter, if amplifier, fsk/ask demodulator, data filter and data slicer. in receive mode the lna pre-amplifies the received signal which is converted down to 226 khz, filtered and amplified before it is fed into an fsk/ask demodulator, data filter and data slicer. the rssi (received signal strength indicator) signal and the raw digital output signal of the demodulator are available at the pins rssi and dem_out. the demodulated data signal demod_out is fed to the digital control logic where it is evaluated and buffered as described in section ?digital control logic? on page 33 . in transmit mode the fractional-n frequency synthesizer generates the tx frequency which is fed to the pa. in ask mode the pa is modulated by the signal pa_enable. in fsk mode the pa is enabled and the signal tx_data (fsk) modulates the fractional-n frequency synthesizer. the frequency deviation is digitally controlled and internally fixed to about 16 khz (see table 6-1 on page 25 for exact values). the transmit data can also be buffered as described in section ?digital control logic? on page 33 . a lock detector within the synthesiz er ensures that the transmission will only start if the synthesizer is locked. the rx/tx switch can be used to combine the lna input and the pa output to a single antenna with a minimum of losses. transparent modes without buffering of rx and tx data are also available to allow protocols and coding schemes other than the in ternal supported manchester encoding. 5.1 low-if receiver the receive path consists of a fully integrated low- if receiver. it fulfills the sensitivity, blocking, selectivity, supply voltage and supply current specification needed to manufacture an automo- tive key fob without the use of saw blocking filter (see figure 2-1 on page 6 ). the receiver can be connected to the roof antenna in the car when using an additional blocking saw front-end fil- ter as shown in figure 3-1 on page 7 . at 433.92 mhz the receiver has a typical system noise figure of 7.0 db, a system i1dbcp of -30 dbm and a system iip3 of ?20 dbm. there is no agc or switching of the lna needed, thus, a better blocking performance is achieved. this re ceiver uses an if (intermediate frequency) of 226 khz, the typical image rejection is 30 db and the typical 3 db if filter bandwidth is 185 khz (f if = 226 khz 92.5 khz, f lo_if = 133.5 khz and f hi_if = 318.5 khz). the demodulator needs a signal to gaussian noise ratio of 8 db for 20 kbit /s manchester with 16 khz frequency deviation in fsk mode, thus, the resulting sensitivity at 433.92 mhz is typically ?106 dbm at 20 kbit/s manchester. due to the low phase noise and spurious of the synthesizer in receive mode (1) together with the eighth order integrated if filter the receiver has a better selectivity and blocking performance than more complex double superhet receivers but without external components and without numerous spurious receiving frequencies. a low-if architecture is also less sensitive to second-order intermodulation (iip2) than direct conversion receivers where every pulse or am-modulated signal (espec ially the signals from tdma systems like gsm) demodulates to the receiving signal band at second-order non-linearities. note: 1. ?120 dbc/hz at 1 mhz and ?75 dbc at fref at 433.92 mhz
10 4689f?rke?08/06 ata5811/ata5812 5.2 input matching at rf_in the measured input impedances as well as the val ues of a parallel equivalent circuit of these impedances can be seen in table 5-1 . the highest sensitivity is achieved with power matching of these impedances to the source impedance of 50 ? . the matching of the lna input to 50 ? was done with the circuit according to figure 5-1 and with the values given in table 5-2 . the reflection coefficients were always 10 db. note that value changes of c 1 and l 1 may be necessary to for compensate individual board layouts. the mea- sured typical fsk and ask manchester code sensitivities wit h a bit error rate (ber) of 10 -3 are shown in table 5-3 on page 11 and table 5-4 on page 11 . these measurements were done with inductors having a quality factor according to table 5-2 , resulting in estimated matching losses of 1.0 db at 315 mhz, 1.2 db at 433.92 mhz and 0.6 db at 868.3 mhz. these losses can be estimated when calculating the parallel eq uivalent resistance of the inductor with r loss =2 f l q l and the matching loss with 10 log(1+r p /r loss ). with an ideal inductor, for example, the sensitivity at 433.92 mhz/fsk/20 kbit/s/ 16 khz/manchester can be improved from ?106 dbm to ?107.2 dbm. the sensitivity depends on the control logic which examines the incomi ng data stream. the examination limits must be programmed in control registers 5 and 6. the measurements in table 5-3 and table 5-4 on page 11 are based on the values of registers 5 and 6 according to table 11-3 on page 58 . figure 5-1. input matching to 50 ? table 5-1. measured input impedances of the rf_in pin f rf /mhz z(rf_in) r p //c p 315 (44-j233) ? 1278 ? //2.1 pf 433.92 (32-j169) ? 925 ? //2.1 pf 868.3 (21-j78) ? 311 ? //2.2 pf table 5-2. input matching to 50 ? f rf /mhz c 1 /pf l 1 /nh q l1 315 2.2 56 43 433.92 1.8 27 40 868.3 1.2 6.8 58 rf in l 1 4 rf_in ata5811/ata5812 c 1
11 4689f?rke?08/06 ata5811/ata5812 5.3 sensitivity versus supply volt age, temperature and frequency offset to calculate the behavior of a tr ansmission system it is important to know the reduction of the sensitivity due to several influences. the most important are frequency offset due to crystal oscillator (xto) and crystal frequency (xtal) errors, temperature and supply voltage depen- dency of the noise figure and if filter bandwidth of the receiver. figure 5-2 shows the typical sensitivity at 433.92 mhz/fsk/20 kbit/s/16 khz/manchester versus the frequency offset between transmitter and receiver with t amb = ?40c, +25c and +105c and supply voltage vs1 = vs2 = 2.4v, 3.0v and 3.6v. figure 5-2. measured sensitivity 433.92 mhz/fsk/20 kbit/s/16 khz/manchester versus frequency offset, tempera- ture and supply voltage table 5-3. measured sensitivity fsk, 16 khz, manchester, dbm, ber = 10 -3 rf frequency br_range_0 1.0 kbit/s br_range_0 2.4 kbit/s br_range_1 5.0 kbit/s br_range_2 10 kbit/s br_range_3 20 kbit/s 315 mhz ?110.0 dbm ?110.5 dbm ?109.0 dbm ?108.0 dbm ?107.0 dbm 433.92 mhz ?109.0 dbm ?109.5 dbm ?108.0 dbm ?107.0 dbm ?106.0 dbm 868.3 mhz ?106.0 dbm ?106.5 dbm ?105.5 dbm ?104.0 dbm ?103.5 dbm table 5-4. measured sensitivity 100% ask, manchester, dbm, ber = 10 -3 rf frequency br_range_0 1.0 kbit/s br_range_0 2.4 kbit/s br_range_1 5.0 kbit/s br_range_2 10 kbit/s 315 mhz ?117.0 dbm ?117.5 dbm ?115 dbm ?113.5 dbm 433.92 mhz ?116.0 dbm ?116.5 dbm ?114.0 dbm ?112.5 dbm 868.3 mhz ?112.5 dbm ?113.0 dbm ?111.5 dbm ?109.5 dbm -110.0 -109.0 -108.0 -107.0 -106.0 -105.0 -104.0 -103.0 -102.0 -101.0 -100.0 -99.0 -98.0 -97.0 -96.0 -95.0 -100 -80 -60 -40 -20 0 20 40 60 80 100 fre q uenc y offset ( khz ) v s = 2.4v, t amb = -40?c sensitivity (dbm) v s = 3.0v, t amb = -40?c v s = 3.6v, t amb = -40?c v s = 2.4v, t amb = +25?c v s = 3.0v, t amb = +25?c v s = 3.6v, t amb = +25?c v s = 2.4v, t amb = +105?c v s = 3.0v, t amb = +105?c v s = 3.6v, t amb = +105?c
12 4689f?rke?08/06 ata5811/ata5812 as can be seen in figure 5-2 on page 11 the supply voltage has almost no influence. the tem- perature has an influence of about +1.5/?0.7 db and a frequency offset of 65 khz also influences by about 1 db. all these influences, co mbined with the sensitivit y of a typical ic, are then within a range of ?103.7 dbm and ?107.3 dbm over temperature, supply voltage and fre- quency offset which is ?105.5 dbm 1.8db. the integrated if filter has an additional production tolerance of only 7 khz, hence, a frequency offs et between the receiver and the transmitter of 58 khz can be accepted for xtal and xto tolerances. note: for the demodulator used in the ata5811/ ata5812, the tolerable frequency offset does not change with the data frequency, he nce, the value of 58 khz is valid for up to 1 kbit/s. this small sensitivity spread over supply voltage, frequency offset and temperature is very unusual in such a receiver. it is achieved by an internal, very fast and automatic frequency cor- rection in the fsk demodulator after the if filter, which leads to a higher system margin. this frequency correction tracks the input frequency very quickly, if however, the input frequency makes a larger step (e.g., if the system changes between different communication partners), the receiver has to be restarted. this can be done by switching back to idle mode and then again to rx mode. for that purpose, an automatic mode is also available. this automatic mote switches to idle mode and back into rx mode every time a bit error occurs (see section ?digital control logic? on page 33 ). 5.4 frequency accurac y of the crystals the xto is an amplitude regulate d pierce oscillator with integrated load capacitors. the initial tolerances (due to the frequency tolerance of the xtal, the integrated capacitors on xtal1, xtal2 and the xto?s initial transconductance gm) can be compensated to a value within 0.5 ppm by measuring the clk output frequency and programming the control registers 2 and 3 (see table 9-7 on page 36 and table 9-10 on page 36 ). the xto then has a remaining influ- ence of less than 2 ppm over temperature and supply voltage due to the bandgap controlled gm of the xto. the needed frequency stability of the used crystals over temperature and aging is hence 58khz/433.92mhz?2 2.5 ppm = 128.66 ppm for 433.92 mhz and 58 khz/868.3 mhz ? 2 2.5 ppm = 61.8 ppm for 868.3 mhz. thus, the used crystals in receiver and transmitter each need to be better than 64.33 ppm for 433.92 mhz and 30.9 ppm for 868.3 mhz. in access control systems it may be advantageous to have a more tight tolerance at the base-station in order to relax the requirement for the key fob. 5.5 rx supply current versus tem perature and supply voltage table 5-5 shows the typical supply current at 433.92 mhz of the transceiver in rx mode versus supply voltage and temperature with vs = vs1 = vs2. as you can see the supply current at 2.4v and ?40c is less than the typical one which helps because this is also the operation point where a lithium cell has the worst performanc e. the typical supply current at 315 mhz or 868.3 mhz in rx mode is about the same as for 433.92 mhz. table 5-5. measured 433.92 mhz receive supply current in fsk mode vs = 2.4 v 3.0 v 3.6 v t amb = ?40c 8.4 ma 8.8 ma 9.2 ma t amb = 25c 9.9 ma 10.3 ma 10.8 ma t amb = 105c 11.4 ma 11.9 ma 12.4 ma
13 4689f?rke?08/06 ata5811/ata5812 5.6 blocking, selectivity as can be seen in figure 5-3 and figure 5-4 , the receiver can receive signals 3 db higher than the sensitivity level in presence of very large blockers of ?47 dbm/?34 dbm with small frequency offsets of 1 / 10 mhz. figure 5-3 shows narrow band blocking and figure 5-4 wide band blocking characteristics. the measurements were done with a useful signal of433.92 mhz/fsk/20 kbit/s/ 16 khz/manches- ter with a level of ?106 dbm + 3 db = ?103 dbm which is 3 db above the sensitivity level. the figures show how much a continuous wave signal can be larger than ?103 dbm until the ber is higher than 10 -3 . the measurements were done at the 50 ? input according to figure 5-1 on page 10 . at 1 mhz, for example, the blocker c an be 56 db higher than ?103 dbm which is ?103 dbm + 56 db = ?47 dbm. these values, together with the good intermodulation perfor- mance, avoid the need for a saw filter in the key fob application. figure 5-3. narrow band 3 db blocking characteristic at 433.92 mhz figure 5-4. wide band 3 db blocking characteristic at 433.92 mhz -10,0 0,0 10,0 20,0 30,0 40,0 50,0 60,0 70,0 -5,0 -4,0 -3,0 -2,0 -1,0 0,0 1,0 2,0 3,0 4,0 5, 0 distance of interferin g to receivin g si g nal [ mhz ] blocking level [dbc] -10,0 0,0 10,0 20,0 30,0 40,0 50,0 60,0 70,0 80,0 -50,0 -40,0 -30,0 -20,0 -10,0 0,0 10,0 20,0 30,0 40,0 50, 0 distance of interfering to receiving signal [mhz] blocking level [dbc]
14 4689f?rke?08/06 ata5811/ata5812 figure 5-5 shows the blocking measurement close to the received frequency to illustrate the selectivity and image rejection. this measurement was done 6 db above the sensitivity level with a useful signal of 433.92 mhz/fsk/20 kbit/s/16 khz/ manchester with a level of ?106 dbm + 6 db = ?100 dbm. the figure shows to wh ich extent a continuous wave signal can surpass ?100 dbm until the ber is higher than 10 -3 . for example, at 1 mhz the blocker can than be 59 db higher than ?100 dbm which is ?100 dbm + 59 db = ?41 dbm. table 5-6 shows the blocking performance measured relative to ?100 dbm for some other fre- quencies. note that sometimes the blocking is measured relative to the sensitivity level (dbs) instead of the carrier (dbc). the ata5811/ata5812 can also receive fsk and ask modulated signals if they are much higher than the i1dbcp. it can typically receive usef ul signals at 10 dbm. this is often referred to as the nonlinear dynamic range which is the maximum to minimum receiving signal which is 116 db for 20 kbit/s manchester. this value is useful if two transceivers have to communicate and are very close to each other. figure 5-5. close in 6 db blocking characteristic and image response at 433.92 mhz table 5-6. blocking 6 db above sensitivity level with ber < 10 -3 frequency offset blocker level blocking +0.75 mhz ?45 dbm 55 dbc/61 dbs ?0.75 mhz ?45 dbm 55 dbc/61 dbs +1.5 mhz ?38 dbm 62 dbc/68 dbs ?1.5 mhz ?38 dbm 62 dbc/68 dbs +10 mhz ?30 dbm 70 dbc/76 dbs ?10 mhz ?30 dbm 70 dbc/76 dbs -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 distance of interfering to receiving signal [mhz] blocking level [dbc]
15 4689f?rke?08/06 ata5811/ata5812 this high blocking performance makes it even possible for some applications using quarter wave whip antennas to use a simple lc band-pass filter instead of a saw filter in the receiver. when designing such an lc filter take into account that the 3 db blocking at 433.92 mhz/2 = 216.96 mhz is 43 dbc and at 433.92 mhz/3 = 144.64 mhz is 48 dbc and at 2 (433.92 mhz + 226 khz) + ?226 khz = 868.066 mhz/868.518 mhz is 56 dbc. and espe- cially that at 3 (433.92 mhz + 226 khz)+226 khz = 1302.664 mhz the receiver has its second lo harmonic receiving frequency with only 12 dbc blocking. 5.7 inband disturbers, data filter, quasi peak detector, data slicer if a disturbing signal falls into the received band or a blocker is not continuous wave the perfor- mance of a receiver strongly depends on the circui ts after the if filter. hence the demodulator, data filter and data slicer are important in that case. the data filter of the ata5811/ata5812 implies a quasi peak detector. this results in a good suppression of the above mentioned disturbers and exhibits a good carrier to gaussian noise performance. the required useful signal to disturbing signal ratio to be received with a ber of 10 -3 is less than 12 db in ask mode and less than 3 db (br_range_0 ... br_range_2)/6 db (br_range_3) in fsk mode. due to the many different waveforms possible these numbers are measured for signal as well as for disturbers with peak amplitude values. note that these values are worst case values and are valid for any type of modulation and modulating frequency of the disturbing signal as well as the receiving signal . for many combinations, lower carrier to disturb- ing signal ratios are needed. 5.8 dem_out output the internal raw output signal of the demodulat or demod_out is available at pin dem_out. dem_out is an open drain output and must be connected to a pull-up resistor if it is used (typi- cally 100 k ? ) otherwise no signal is present at that pin. 5.9 rssi output the output voltage of the pin rssi is an analog voltage, proportional to the input power level. using the rssi output signal, the signal strength of different transmitters can be distinguished. the usable dynamic range of the rssi amplifier is 70 db, the input power range p(rf in ) is ?115 dbm to ?45 dbm and the gain is 8 mv/db. figure 5-6 on page 16 shows the rssi charac- teristic of a typical device at 433.92 mhz with vs1 = vs2 = 2.4 v to 3.6 v and t amb = ?40c to +105c with a matched input according to table 5-2 on page 10 and figure 5-1 on page 10 . at 868.3 mhz about 2.7 db more signal level and at 315 mhz about 1 db less signal level is needed for the same rssi results.
16 4689f?rke?08/06 ata5811/ata5812 figure 5-6. typical rssi characteristic versus temperature and supply voltage 5.10 frequency synthesizer the synthesizer is a fully integrated fractional-n design with internal loop filters for receive and transmit mode. the xto frequency f xto is the reference frequency fref for the synthesizer. the bits fr0 to fr8 in control registers 2 and 3 (see table 9-7 on page 36 and table 9-10 on page 36 ) are used to adjust the deviation of f xto . in transmit mode, at 433.92 mhz, the carrier has a phase noise of ? 111 dbc/hz at 1 mhz and spurious at fref of ? 66 dbc with a high pll loop bandwidth allowing the direct modulation of the carrier with 20 kbit/s manchester data. due to the closed loop modulation any spurious caused by this modulation are effectively filtered out as can be seen in figure 5-9 on page 18 . in rx mode the synthesizer has a phase noise of ?120 dbc/hz at 1 mhz and spurious of ? 75 dbc. the initial tolerances of the crystal oscillator due to crystal tolerances, internal capacitor toler- ances and the parasitics of the board have to be compensated at manufacturing setup with control registers 2 and 3 as can be seen in table 6-1 on page 25 . the other control words for the synthesizer needed for ask, fsk and receive/transmit switching are calculated internally. the rf (radio frequency) resolution is equal to the xto frequency divided by 16384 which is 777.1 hz at 315.0 mhz, 808.9 hz at 433.92 mhz and 818.59 hz at 868.3 mhz. 5.11 fsk/ask transmission due to the fast modulation capability of the synthesizer and the high resolution, the carrier can be internally fsk modulated which simplifies the application of the transceiver. the deviation of the transmitted signal is 20 digital frequency steps of the synthesizer which is equal to 15.54 khz for 315 mhz, 16.17 khz for 433.92 mhz and 16.37 khz for 868.3 mhz. due to closed loop modulation with pll filtering the modulated spectrum is very clean, meeting etsi and cept regulations when using a simple lc filter for the power amplifier harmonics as it is shown in figure 3-1 on page 7 . in ask mode the frequency is in ternally connec ted to the cen- ter of the fsk transmission and the power amp lifier is switched on and off to perform the modulation. figure 5-7 on page 17 to figure 5-9 on page 18 show the spectrum of the fsk mod- ulation with pseudo random data with 20 kbit/s/16.17 khz/manchester and 5 dbm output power. 400 500 600 700 800 900 1000 1100 -120 -110 -100 -90 -80 -70 -60 -50 -40 prf_in (dbm) v rssi (mv) typ. min. max.
17 4689f?rke?08/06 ata5811/ata5812 figure 5-7. fsk-modulated tx spectrum (20 kbit/s/ 16.17 khz/manchester code) figure 5-8. unmodulated tx spectrum f fsk_l ref 10 dbm atten 20 db samp log 10 db/ vavg 50 w1 s2 s3 fc center 433.92 mhz res bw 100 khz vbw 100 khz span 30 mhz sweep 7.5 ms (401 pts) sweep 27.5 ms (401 pts) ref 10 dbm samp log 10 db/ vavg 50 w1 s2 s3 fc atten 20 db center 433.92 mhz res bw 10 khz span 1 mhz vbw 10 khz
18 4689f?rke?08/06 ata5811/ata5812 figure 5-9. fsk-modulated tx spectrum (20 kbit/s/ 16.17 khz/manchester code) 5.12 output power setting and pa matching at rf_out the power amplifier (pa) is a single-ended open collector stage which delivers a current pulse which is nearly independent of supply voltage, temperature and tolerances due to bandgap sta- bilization. resistor r 1 , see figure 5-10 on page 19 , sets a reference current which controls the current in the pa. a higher resistor value results in a lower reference current, a lower output power and a lower current consumption of the pa. the usable range of r 1 is 15 k ? to 56 k ? . pin pwr_h switches the output power range between about 0 dbm to 5 dbm (pwr_h = gnd) and 5 dbm to 10 dbm (pwr_h = avcc) by multiplying this reference current with a factor 1 (pwr_h = gnd) and 2.5 (pwr_h = avcc) which corresponds to about 5 db more output power. if the pa is switched off in tx mode, the current consumption without output stage with vs1 = vs2 = 3v, t amb = 25c is typically 6.5 ma for 868.3 mhz and 6.95 ma for 315 mhz and 433.92 mhz. the maximum output power is achieved with optimum load resistances r lopt according to table 5-7 on page 20 with compensation of the 1.0 pf output capacitance of the rf_out pin by absorbing it into the matching network consisting of l 1 , c 1 , c 3 as shown in figure 5-10 on page 19 . there must be also a low resistive dc path to avcc to deliver the dc current of the power amplifier's last stage. the matching of the pa output was done with the circuit according to fig- ure 5-10 on page 19 with the values in table 5-7 on page 20 . note that value changes of these elements may be necessary to compensate for individual board layouts. ref 10 dbm atten 20 db samp log 10 db/ vavg 50 w1 s2 s3 fc center 433.92 mhz res bw 10 khz vbw 10 khz span 1 mhz sweep 27.5 ms (401 pts)
19 4689f?rke?08/06 ata5811/ata5812 example: according to table 5-7 on page 20 , with a frequency of 433.92 mhz and output power of 11 dbm the overall current consumption is typically 17.8 ma hence the pa needs 17.8 ma - 6.95 ma = 10.85 ma in this mode which corresponds to an overall power amplifier efficiency of the pa of (10 (11dbm/10) 1mw)/(3v 10.85 ma) 100% = 38.6% in this case. using a higher resistor in this example of r 1 =1.091 22 k ? =24k ? results in 9.1% less cur- rent in the pa of 10.85 ma/1.091 = 9.95 ma and 10 log(1.091) = 0.38 db less output power if using a new load resistance of 300 ? 1.091 = 327 ? . the resulting output power is then 11 dbm ? 0.38 db = 10.6 dbm and the overall current consumption is 6.95 ma + 9.95 ma = 16.9 ma. the values of table 5-7 on page 20 were measured with standard multi-layer chip inductors with quality factors q according to table 5-7 on page 20 . looking to the 433.92 mhz/11 dbm case with the quality factor of q l1 = 43 the loss in this inductor is estimated with the parallel equiva- lent resistance of the inductor r loss =2 f l q l1 and the matching loss with 10 log (1 + r lopt /r loss ) which is equal to 0.32 db losses in th is inductor. taking this into account the pa efficiency is then 42% instead of 38.6%. be aware that the high power mode (pwr_h = avcc) can only be used with a supply voltage higher than 2.7v, whereas the low power mode (pwr_h = gnd) can be used down to 2.4v as can be seen in the section ?electrical characteristics: general? on page 63 . the supply blocking capacitor c 2 (10 nf) has to be placed close to the matching network because of the rf current flowing through it. figure 5-10. power setting and output matching rf out 10 rf_out vpwr_h avcc ata5811/ata5812 9 pwr_h 8 r_pwr c 2 c 1 l 1 c 3 r 1
20 4689f?rke?08/06 ata5811/ata5812 5.13 output power and tx supply current versus supply voltage and temperature table 5-8 on page 20 shows the measurement of the output power for a typical device with vs1 = vs2 = vs in the 433.92 mhz and 6.2 dbm case versus temperature and supply voltage measured according to figure 5-10 on page 19 with components according to table 5-7 . as opposed to the receiver sensitivity the supply voltage has here the major impact on output power variations because of the large signal behavior of a power amplifier. thus, a two battery system with voltage regulator or a 5v system shows much less variation than a 2.4v to 3.6v one battery system because the supply voltage is then well within 3.0v and 3.6v. the reason is that the amplitude at the output rf_out with optimum load resistance is avcc ? 0.4v and the power is proportional to (avcc ? 0.4v) 2 if the load impedance is not changed. this means that the theoretical output power reduction if reducing the supply voltage from 3.0v to 2.4v is 10 log ((3v ? 0.4v) 2 /(2.4v ? 0.4v) 2 ) = 2.2 db. table 5-8 shows that principle behavior in the measurement. this is not the same case for higher voltages since here increas- ing the supply voltage from 3v to 3.6v should theoretical increase the power by 1.8 db but only 0.8 db in the measurement shows that the amplitude does not increase with the supply voltage because the load impedance is optimized for 3v and the output amplitude stays more constant. table 5-9 on page 21 shows the relative changes of the output power of a typical device com- pared to 3.0v/25c. as can be seen a temperature change to ? 40 as well as to +105 reduces the power by less than 1 db due to the bandgap regulated output current. measurements of all the cases in table 5-7 on page 20 over temperature and supply voltage have shown about the same relative behavior as shown in table 5-9 on page 21 . table 5-7. measured output power and current consumption with vs1 = vs2 = 3 v, t amb = 25c frequency (mhz) tx current (m a) output power (dbm) r1 (k ? ) vpwr_h r lopt ( ? )l1 (nh) q l1 c1 (pf) c3 (pf) 315 8.5 0.4 56 gnd 2500 82 28 1.5 0 315 10.5 5.7 27 gnd 920 68 32 2.2 0 315 16.7 10.5 27 avcc 350 56 35 3.9 0 433.92 8.6 0.1 56 gnd 2300 56 40 0.75 0 433.92 11.2 6.2 22 gnd 890 47 38 1.5 0 433.92 17.8 11 22 avcc 300 33 43 2.7 0 868.3 9.3 ?0.3 33 gnd 1170 12 58 1.0 3.3 868.3 11.5 5.4 15 gnd 471 15 54 1.0 0 868.3 16.3 9.5 22 avcc 245 10 57 1.5 0 table 5-8. measured output power and supply current at 433.92 mhz, pwr_h = gnd vs = 2.4 v 3.0 v 3.6 v t amb = ?40c 10.19 ma 3.8 dbm 10.19 ma 5.5 dbm 10.78 ma 6.2 dbm t amb = +25c 10.62 ma 4.6 dbm 11.19 ma 6.2 dbm 11.79 ma 7.1 dbm t amb = +105c 11.4 ma 3.8 dbm 12.02 ma 5.4 dbm 12.73 ma 6.3 dbm
21 4689f?rke?08/06 ata5811/ata5812 5.14 rx/tx switch the rx/tx switch decouples the lna from the pa in tx mode, and directs the received power to the lna in rx mode. to do this, it has a low impedance to gnd in tx mode and a high impedance to gnd in rx mode. to design a proper rx/tx decoupling a linear simulation tool for radio frequency design together with the measured device impedances of table 5-1 on page 10 , table 5-7 on page 20 , table 5-10 and table 5-11 on page 22 should be used, but the exact element values have to be found on board. figure 5-11 on page 21 shows an approximate equivalent circuit of the switch. the principal switching operation is described here according to the application of figure 2-1 on page 6 . the application of figure 3-1 on page 7 works similarly. figure 5-11. equivalent circuit of the switch table 5-9. measurements of typical output power relative to 3v/25 vs = 2.4v 3.0v 3.6v t amb = ?40c ?2.4 db ?0.7 db 0 db t amb = +25c ?1.6 db 0 db +0.9 db t amb = +105c ?2.4 db ?0.8 db +0.1 db table 5-10. impedance of the rx/tx switch rx_tx2 shorted to gnd frequency z(rx_tx1) tx mode z(rx_tx1) rx mode 315 mhz (4.8 + j3.2) ? (11.3 ? j214) ? 433.92 mhz (4.5 + j4.3) ? (10.3 ? j153) ? 868.3 mhz (5 + j9) ? (8.9 ? j73) ? 1.6 nh 2.5 pf rx_tx1 tx 11 ? 5 ?
22 4689f?rke?08/06 ata5811/ata5812 5.15 matching network in tx mode in tx mode the 20 mm long and 0.4 mm wide transmission line which is much shorter than /4 is approximately switched in parallel to the capacitor c 9 to gnd. the antenna connection between c 8 and c 9 has an impedance of about 50 ? locking from the transmission line into the loop antenna with pin rf_out, l 2 , c 10 , c 8 and c 9 connected (using a c 9 without the added 7.6 pf as discussed later). the transmission line can be approximated with a 16 nh inductor in series with a 1.5 ? resistor, the closed switch can be approximated according to table 5-10 on page 21 with the series connection of 1.6 nh and 5 ? in this mode. to have a parallel resonant high impedance circuit with little rf power going into it looking from the loop antenna into the trans- mission line a capacitor of about 7.6 pf to g nd is needed at the beginning of the transmission line (this capacitor is later absorbed into c 9 which is then higher as needed for 50 ? transforma- tion). to keep the 50 ? impedance in rx mode at the end of this transmission line c 7 has to be also about 7.6 pf. this reduces the tx power by about 0.5 db at 433.92 mhz compared to the case the where the lna path is completely disconnected. 5.16 matching network in rx mode in rx mode the rf_out pin has a high impedance of about 7 k ? in parallel with 1.0 pf at 433.92 mhz as can be seen in table 5-11 on page 22 . this together with the losses of the inductor l 2 with 120 nh and q l2 = 25 gives about 3.7 k ? loss impedance at rf_out. since the optimum load impedance in tx mode for the power amplifier at rf_out is 890 ? the loss asso- ciated with the inductor l 2 and the rf_out pin can be estimated to be 10 log(1 + 890/3700) = 0.95 db compared to the optimum matched loop antenna without l 2 and rf_out. the switch represents, in this mode at 433.92 mhz, about an inductor of 1.6 nh in series with the parallel connection of 2.5 pf and 2.0 k ? . since the impedance level at pin rx_tx1 in rx mode is about 50 ? this only negligiblably dampens the received signal by about 0.1 db. when matching the lna to the loop antenna the transmission line and the 7.6 pf part of c 9 has to be taken into account when choosing the values of c 11 and l 1 so that the impedance seen from the loop antenna into the transmission line with the 7.6 pf capacitor connected is 50 ? . since the loop antenna in rx mode is loaded by the lna input impedance the loaded q of the loop antenna is lowered by about a factor of 2 in rx mode hence the antenna bandwidth is higher than in tx mode. note that if matching to 50 ? , like in figure 3-1 on page 7 , a high q wire wound inductor with a q > 70 should be used for l 2 to minimize its contribution to rx losses which will otherwise be dominant. the rx and tx losses will be in the range of 1.0 db there. table 5-11. impedance rf_out pin in rx mode frequency z(rf_out)rx r p //c p 315 mhz 36 ? ? j 502 ? 7 k ?/ / 1.0 pf 433.92 mhz 19 ? ? j 366 ? 7 k ?/ / 1.0 pf 868.3 mhz 2.8 ? ? j 141 ? 7 k ?/ / 1.3 pf
23 4689f?rke?08/06 ata5811/ata5812 6. xto the xto is an amplitude regulated pierce oscillator type with integrated load capacitances (2 18 pf with a tolerance of 17%) hence c lmin = 7.4 pf and c lmax = 10.6 pf. the xto oscil- lation frequency f xto is the reference frequency fref for the fractional-n synthesizer. when designing the system in terms of receiving and transmitting frequency offset the accuracy of the crystal and xto have to be considered. the synthesizer can adjust the local osc illator frequency for more than 150 ppm at 433.92 mhz/315 mhz and up to 118 ppm at 868.3 mhz of initial frequency error in f xto . this is done at nominal supply voltage and temperature with the control registers 2 and 3 (see table 9-7 on page 36 and table 9-10 on page 36 ). the remaining local osc illator tolerance at nominal supply voltage and temperature is then < 0.5 ppm. a xto frequency error of 150 ppm/118 ppm can hence be tolerated due to the crystal tolerance at 25c and the toler- ances of c l1 and c l2 . the xto?s gm has very low influence of less than 2 ppm on the frequency at nominal supply voltage and temperature. over temperature and supply voltage, the xto's additional pulling is only 2 ppm if c m 7ff. the xtal versus temperature and its aging is then the main source of frequency error in the local oscillator. the xto frequency depends on xtal properties and the load capacitances c l1, 2 at pin xtal1 and xtal2. the pulling of f xto from the nominal f xtal is calculated using the following formula: ppm. c m is the crystal's motional, c 0 the shunt and c ln the nominal load capacitance of the xtal found in its data sheet. c l is the total actual load capacitance of the crystal in the circuit and con- sists of c l1 and c l2 in series connection. figure 6-1. xtal with load capacitance with c m 14 ff, c 0 1.5 pf, c ln = 9 pf and c l = 7.6 pf to 10.6 pf the pulling amounts to p 100 ppm and with c m 7ff, c 0 1.5 pf, c ln = 9 pf and c l = 7.4 pf to 10.6 pf the pulling is p 50 ppm. since typical crystals have less than 50 ppm tolerance at 25 the compensation is not critical. c 0 of the xtal has to be lower than c lmin /2 = 3.8 pf for a pierce oscillator type in order to not enter the steep region of pulling versus load capacitance where there is a risk of an unstable oscillation. p c m 2 ------- - c ln c l ? c 0 c ln + () c 0 c l + () ------------------------------------------------------------- 10 6 = c 0 c l2 c l1 c m l m r m c l = c l1 c l2 / (c l1 + c l2 ) xtal crystal equivalent circuit
24 4689f?rke?08/06 ata5811/ata5812 to ensure proper start-up behavior the small signal gain and thus the negative resistance pro- vided by this xto at start is ve ry large, for example oscillation st arts up even in worst case with a crystal series resistance of 1.5 k ? at c 0 2.2 pf with this xto. the negative resistance is approximately given by with z 1 , z 2 as complex impedances at pin xtal1 and xtal2 hence z1 = ?j/(2 f xto c l1 )+5 ? and z2 = ?j/(2 f xto c l2 ) + 5 ? . z 3 consists of crystals c 0 in parallel with an internal 110 k ? resistor hence z3 = ?j/(2 f xto c 0 )/110k ? , gm is the internal transconductance between xtal1 and xtal2 with typically 19 ms at 25c. with f xto = 13.5 mhz, gm = 19 ms, cl = 9 pf, c 0 = 2.2 pf this results in a negative resistance of about 2 k ? . the worst case for technological, supply voltage and temperature variations is then for c 0 2.2 pf always higher than 1.5 k ? . due to the large gain at start the xto is able to meet a very low start-up time. the oscillation start-up time can be estimated with the time constant . after 10 to 20 an amplitude detector detects the oscillation amplitude and sets xto_ok to high if the amplitude is large en ough, this sets n_r eset to high and activa tes the clk output if clk_on in control register 3 is high (see table 9-7 on page 36 ). note that th e necessary condi- tions of the vsout and dvcc voltage also have to be fulfilled (see figure 6-2 on page 25 and figure 7-1 on page 27 ). to save current in idle and sleep mode, the load capacitors partially are switched off in this modes with s1 and s2 seen in figure 6-2 on page 25 . it is recommended to use a crystal with c m = 4.0 ff to 7.0 ff, c ln =9 pf, r m <120 ? and c 0 = 1.5 pf to 2.2 pf. re z xtocore {} re z 1 z 3 z 2 z 3 z 1 + z 2 z 3 g m + z 1 z 2 z 3 z 1 z 2 g m +++ ----------------------------------------------------------------------------------------------------- - ?? ?? ?? = 2 4 2 f m 2 c m re z xtocore () r m + () ------------------------------------------------------------------------------------------------------- - =
25 4689f?rke?08/06 ata5811/ata5812 figure 6-2. xto block diagram to find the right values used in the control registers 2 and 3 (see table 9-7 on page 36 and table 9-10 on page 36 ) the relationship between f xto and the f rf is shown in table 6-1 . to determine the right content the frequency at pin clk as well as the output frequency at rf_out in ask mode can be measured , than the freq value can be calculated according to table 6-1 so that f rf is exactly the desired radio frequency 8 pf 8 pf xtal1 divider /16 clk_on (control register 3) vsout_ok (from power supply) dvcc_ok (from power supply) baud1 in idle mode and during sleep mode (rx_polling) the switches s1 and s2 are open. xlim baud0 & divider /3 xto_ok (to reset logic) divider /1 /2 /4 /8 /16 10 pf 10 pf amplitude detector s2 s1 f xdclk xtal2 clk c l2 c l1 f xto f dclk table 6-1. calculation of f rf frequency (mhz) pin 6 433_n868 creg1 bit(4) fs f xto (mhz) f rf = f tx_ask = f rx f tx_fsk_l f tx_fsk_h 433.92 avcc 0 13.25311 f rf ? 16.17 khz f rf + 16.17 khz 868.3 gnd 0 13.41191 f rf ? 16.37 khz f rf + 16.37 khz 315.0 avcc 1 12.73193 f rf ? 15.54 khz f rf + 15.54 khz f xto 32 5 freq 20,5 + 16384 ---------------------------------- + , ?? ?? f xto 64 5 freq 20,5 + 16384 ---------------------------------- + , ?? ?? f xto 24 5 freq 20,5 + 16384 ---------------------------------- + , ?? ??
26 4689f?rke?08/06 ata5811/ata5812 the variable freq depends on freq2 and freq3, which are defined by the bits fr0 to fr8 in control register 2 and 3 and is calculated as follows: freq = 3584 + freq2 + freq3 only the range of freq = 3803 to 4053 of this register should be used because otherwise har- monics of f xto and f clk can cause interference with the received signals (freq_min = 3803, freq_max = 4053). the resulting tuning range is 118 ppm at 868.3 mhz and more than 150 ppm at 433.92 mhz or 315 mhz. 6.1 pin clk pin clk is an output to clock a connected microcontroller. the clock frequency f clk is calculated as follows: because the enabling of pin clk is asynchronous the first clock cycle may be incomplete. the signal at clk output has a nominal 50% duty cycle. figure 6-3. clock timing 6.2 basic clock cycle of the digital circuitry the complete timing of the digital circuitry is derived from one clock. according to figure 6-2 on page 25 , this clock cycle t dclk is derived from the crystal os cillator (xto) in combination with a divider. t dclk controls the following applic ation relevant parameters: timing of the polling circuit including bit-check tx bit rate f clk f xto 3 ----------- = clk_on (control register 3) n_reset clk vsout v thres_2 = 2.38v (typically) v thres_2 = 2.38v (typically) f dclk f xto 16 ----------- =
27 4689f?rke?08/06 ata5811/ata5812 the clock cycle of the bit-check and the tx bit rate depends on the se lected bit-rate range (br_range) which is defined in control register 6 (see table 9-20 on page 39 ) and xlim which is defined in control register 4 (see table 9-13 on page 37 ). this clock cycle t xdclk is defined by the following formulas for further reference: br_range ? br_range 0: t xdclk = 8 t dclk xlim br_range 1: t xdclk = 4 t dclk xlim br_range 2: t xdclk = 2 t dclk xlim br_range 3: t xdclk = 1 t dclk xlim 7. power supply figure 7-1. power supply v_reg2 3.25v typ. v_monitor (2.3v/ 2.38v typ.) v_monitor (1.5v typ.) v_reg1 3.25v typ. sw_dvcc low_batt (status register and reset logic) vsout_ok (to xto and reset logic) dvcc_ok (to xto and reset logic) sw_vsout vsout_en vaux sw_avcc out t5 vs1+ 0.55v typ. to t1 r s ff1 q pwr_on vsint avcc_en dvcc_ok offcmd p_on_aux (command via spi) (status register) r 0 1 0 1 q no change 0 1 1 s 0 0 1 1 ( control re g ister 3 ) (control register 1) avcc vsout dvcc vs2 vs1 in en out in en and + - 1 1
28 4689f?rke?08/06 ata5811/ata5812 the supply voltage range of the ata5811/ata5812 is 2.4v to 3.6v or 4.4v to 6.6v. pin vs1 is the supply voltage input for the range 2.4v to 3.6v and is used in battery applications using a single lithium 3v cell. pin vs2 is the vo ltage input for the range 4.4v to 6.6v (2 battery application and car applications) in this case the voltage regulator v_reg1 regulates vs1 to typically 3.25 v. if the voltage regulator is acti ve a blocking capacitor of 2.2 f has to be con- nected to vs1. pin vaux is an input for an additi onal auxiliary voltage supply and can be connected e.g., to an inductive supply (see figure 7-6 on page 33 ). this input can only be used together with a recti- fier or as in the application of figure 3-1 on page 7 and must otherwise be left open. pin vsint is the voltage input for the microcontoller_interface and must be connected to the power supply of the microcontroller. the voltage range of v vsint is 2.4v to 5.25v (see figure 7-5 on page 32 and figure 7-6 on page 33 ). avcc is the internal operation voltage of t he rf transceiver and is feed via the switch sw_avcc by vs1. avcc must be blocked with a 68 nf capacitor (see figure 2-1 on page 6 , figure 3-1 on page 7 and figure 4-1 on page 8 ). dvcc is the internal operation voltage of the digital control logic and is feed via the switch sw_dvcc by vs1 or vsout. dvcc must be blocked on pin dvcc with 68 nf (see figure 2-1 on page 6 , figure 3-1 on page 7 and figure 4-1 on page 8 ). pin vsout is a power supply output voltage for external devices (e.g., microcontroller) and is fed via the switch sw_vsout by vs1 or via v_reg2 by the a auxiliary voltage supply vaux. the voltage regulator v_reg2 regulates vsout to typically 3.25v. if the voltage regulator is active a blocking capacitor of 2.2 f has to be connected to vsout. vsout can be switched off by the vsout_en bit in control register 3 and is then reactivated by conditions found in fig- ure 7-2 on page 29 . pin n_reset is set to low if the voltage v vsout at pin vsout drops below 2.3v (typically) and can be used as a reset signal for a connected microcontroller (see figure 7-3 on page 31 and figure 7-4 on page 32 ). pin pwr_on is an input to switch on the transceiver (active high). pin t1 to t5 are inputs for push buttons and can also be used to switch on the transceiver (active low). for current consumption reasons it is recommended to set t1 to t5 to gnd or pwr_on to vcc only temporarily. otherwise an additional current flows. there are two voltage monitors generating the following signals (see figure 7-1 on page 27 ): dvcc_ok if dvcc > 1.5v typically vsout_ok if vsout > v thres1 (2.3v typically) low_batt if vsout < v thres2 (2.38v typically)
29 4689f?rke?08/06 ata5811/ata5812 figure 7-2. flow chart operation modes 7.1 off mode after connecting the power supply (battery) to pin vs1 and/or vs2 and if the voltage on pin vaux v vaux < 3.5v (typically) the transceiver is in off mode. in off mode avcc, dvcc and vsout are disabled, resulting in very low power consumption (i s_off is typically 10 na). in off mode the transceiver is not programmable via the 4-wire serial interface. avcc = vs1 dvcc = vs1 vsout = off idle mode avcc = vs1 dvcc = vs1 vsout = vs1 or v_reg2 tx mode avcc = vs1 dvcc = vs1 vsout = vs1 or v_reg2 avcc = vs1 dvcc = vs1 vsout = vs1 or v_reg2 rx polling mode avcc = vs1 dvcc = vs1 vsout = off rx polling mode aux mode avcc = vs1 dvcc = vs1 vsout = vs1 v vaux > vs1 + 0.5v v vaux < vs1 + 0.5v v vaux > 3.5v (typ) v vaux < 3.5v (typ) idle mode avcc = vs1 dvcc = vs1 vsout = v_reg2 idle mode avcc = vs1 dvcc = vs1 vsout = v_reg2 idle mode avcc = off dvcc = v_reg2 vsout = v_reg2 aux mode pin pwr_on = 1 or pin t1, t2, t3, t4 or pin t5 pin pwr_on = 1 or pin t1, t2, t3, t4 or pin t5 or bit avcc_en = 1 opm1 = 0 and opm0 = 1 opm1 0 1 1 opm0 1 0 1 tx mode rx polling mode rx mode opm1 = 1 and opm0 = 1 or bit check ok vsout_en = 0 bit check ok opm1 = 1 and opm0 = 1 opm1 = 1 and opm0 = 0 opm1 = 1 and opm0 = 0 opm1 = 0 and opm0 = 1 vsout_en = 0 statusbit power_on = 1 or event on pin t1, t2, t3, t4 or t5 statusbit power_on = 1 or event on pin t1, t2, t3, t4 or t5 bit avcc_en = 0 and off command and pin pwr_on = 0 and pin t1, t2, t3, t4 and t5 = 1 bit avcc_en = 0 and off command and pin pwr_on = 0 and pin t1, t2, t3, t4 and t5 = 1
30 4689f?rke?08/06 ata5811/ata5812 7.2 aux mode the transceiver changes from off mode to aux mode if the voltage at pin vaux v vaux >3.5v (typically). in aux mode dvcc and vsout are connected to the auxiliary power supply input (vaux) via the voltage regulator v_reg2. in aux mode the transceiver is programmable via the 4-wire serial interface, but no rx or tx operations are possible because avcc = off. the state transition off mode to aux mode is indicated by an interrupt at pin irq and the sta- tus bit p_on_aux = 1. 7.3 idle mode in idle mode avcc and dvcc are connected to the battery voltage (vs1). from off mode the transceiver changes to idle mode if pin pwr_on is set to 1 or pin t1, t2, t3, t4 or t5 is set to 0. this state transition is indicated by an interrupt at pin irq and the status bits power_on = 1 or st1, st2, st3, st4 or st5 = 1. from aux mode the transceiver changes to id le mode by setting avcc_en = 1 in control register 1 via the 4-wire serial interface or if pin pwr_on is set to 1 or pin t1, t2, t3, t4 or t5 is set to 0. vsout is either connecte d to vs1 or to the auxilia ry power supply (v_reg2). if v vaux < vs1 + 0.5v, vsout is connected to vs1. if v vaux >v s1 + 0.5v, vsout is con- nected to v_reg2 and the status bit p_on_aux is set to 1. in idle mode the rf transceiver is disabled and the power consumption i s_idle is about 230 a (vsout off and clk output off vs1 = vs2 = 3v). the exact value of this current is strongly dependent on the application and the exact operation mode, therefore check the section ?electri- cal characteristics: general? on page 63 for the appropriate application case. via the 4-wire serial interface a connected mi crocontroller can program the required parameter and enable the tx, rx polling or rx mode. the transceiver can be set back to off mode by an off command via the 4-wire serial inter- face (the bit avcc_en must be set to 0, the input level of pin pwr_on must be 0 and pin t1, t2, t3, t4 and t5 = 1 before writing the off command). 7.4 reset timing and reset logic if the transceiver is switched on (off mode to idle mode, off mode to aux mode) dvcc and vsout are ramping up as illustrated in figure 7-3 on page 31 (avcc only ramps up if the trans- ceiver is set to the id le mode). the internal signal dvcc_reset resets the digital control logic and sets the control register to default values. a voltage monitor generates a lo w level at pin n_reset unt il the voltage at pin vsout exceeds 2.38v (typically) and the start-up time of the xto has elapsed (amplitude detector, see figure 6-2 on page 25 ). after the voltage at pin vsout exceeds 2.3v (typically) and the start-up time of the xto has elapsed the output clock at pin clk is available. because the enabling of pin clk is asynchronous the first clock cycle may be incomplete. table 7-1. control register 1 opm1 opm0 function 00idle mode
31 4689f?rke?08/06 ata5811/ata5812 the status bit low_batt is set to 1 if the voltage at pin vsout v vsout drops below v thres_2 (typ- ically 2.38v). low_batt is set to 0 if v vsout exceeds v thres_2 and the status register is read via the 4-wire serial interface or n_reset is set to low. if v vsout drops below v thres_1 (typically 2.3v), n_reset is se t to low. if bit vsout_en in con- trol register 3 is 1, a dvcc_reset is also generated. if v vsout was prior disabled by the connected microcontroller by setting bit vso ut_en = 0, no dvcc_reset is generated. note: if vsout < v thres_1 (typically 2.3v) the output of the pin clk is low, the microcontroller_interface is disabled and the transceiver is not programmable via the 4-wire serial interface. figure 7-3. reset timing n_reset vsout_en (control register 3) low_batt (status register) dvcc_reset clk vsout dvcc (avcc) v thres_1 = 2.3v (typ) 1.5v (typically) v thres_2 = 2.38v (typ) v sout > 2.3v and the xto is running v sout > 2.38v and the xto is running
32 4689f?rke?08/06 ata5811/ata5812 figure 7-4. reset logic, sr latch generates the hysteresis in the nreset signal 7.5 1-battery application the supply voltage range is 2.4v to 3.6v and vaux is not used. figure 7-5. 1-battery application 1 and xto_ok low_batt vsout_ok dvcc_ok vsout_en dvcc_reset n_rese t and and q q r s s 0 0 1 1 r 0 1 0 1 q no change 0 1 no change vs in out in out out in in vsout vsint nreset clk irq cs sck sdi_tmdi sdo_tmdo dvcc rf-transceiver ata5811/ata5812 microcontroller microcontroller_interface digital control logic avcc vaux vs2 2.4v to 3.6v vs1 dem_out
33 4689f?rke?08/06 ata5811/ata5812 7.6 2-battery application the supply voltage range is 4.4v to 6.6v and vaux is connected to an inductive supply. figure 7-6. 2-battery application with inductive emergency supply 8. microcontroller interface the microcontroller interface is a level converter wh ich converts all internal digital signals which are referred to the dvcc voltage, into the voltage used by the microcontroller. therefore, the pin vsint has to be connected to the supply voltage of the microcontroller. this makes it possible to use the internal voltage regulator/switch at pin vsout as in figure 2-1 on page 6 and figure 4-1 on page 8 or to connect the microcontroller and the pin vsint directly to the supply voltage of the microcontroller as in figure 3-1 on page 7 . 9. digital control logic 9.1 register structure the configuration of the transceiver is stored in ram cells. the ram contains a 16 8-bit tx/rx data buffer and a 6 8-bit control register and is write and readable via a 4-wire serial interface (cs, sck, sdi_tmdi, sdo_tmdo). the 1 8-bit status register is not part of the ram and is readable via the 4-wire serial interface. vs in out in out out in in vsout vsint nreset clk irq cs sck sdi_tmdi sdo_tmdo dvcc rf-transceiver ata5811/ata5812 microcontroller microcontroller_interface digital control logic avcc vaux vs2 4.4v to 6.6v vs1 dem_out
34 4689f?rke?08/06 ata5811/ata5812 the ram and the status information is stored as long as the transceiver is in any active mode (dvcc = vs1 or dvcc = v_reg2) and gets lost if the transceiver is in off mode (dvcc = off). after the transceiver is turned on via pin pwr_on = high, t1 = low, t2 = low, t3 = low, t4 = low or t5 = low or the voltage at pin vaux v vaux > 3.5v (typically) the control registers are in the default state. figure 9-1. register structure msb lsb status register (adr 8) control register 1 (adr 0) control register 4 (adr 3) st5 st4 st3 st2 st1 bitchk1 bitchk0 ask/ nfsk sleep4 sleep3 sleep2 sleep1 sleep0 xsleep lim_min5 lim_max5 ir1 ir0 tx/rx data buffer: 16 x 8 bit opm 1 - t_mode control register 5 (adr 4) control register 6 (adr 5) power_ on control register 2 (adr 1) fr4 fr3 fr2 fr1 fr0 control register 3 (adr 2) ----fr8 low_ batt p_on_ aux fs avcc_ en fr5 fr6 fr7 vsout_ en clk_on xlim baud1 baud0 opm 0 p_mode lim_min0 lim_min1 lim_min2 lim_min3 lim_min4 lim_max0 lim_max1 lim_max2 lim_max3 lim_max4
35 4689f?rke?08/06 ata5811/ata5812 9.2 tx/rx data buffer the tx/rx data buffer is used to handle the data transfer during rx and tx operations. 9.3 control register to use the transceiver in different applications it can be configured by a connected microcontrol- ler via the 4-wire serial interface. 9.3.1 control register 1 (adr 0) table 9-1. control register 1 (function of bit 7 and bit 6 in rx mode) ir1 ir0 function (rx mode) 00 pin irq is set to 1 if 4 received bytes are in the tx/rx data buffer or a receiving error occurred 01 pin irq is set to 1 if 8 received bytes are in the tx/rx data buffer or a receiving error occurred 10 pin irq is set to 1 if 12 received bytes are in the tx/rx data buffer or a receiving error occurred (default) 1 1 pin irq is set to 1 if a receiving error occurred table 9-2. control register 1 (function of bit 7 and bit 6 in tx mode) ir1 ir0 function (tx mode) 0 0 pin irq is set to 1 if 4 bytes still are in the tx /rx data buffer or the tx data buffer is empty 0 1 pin irq is set to 1 if 8 bytes still are in the tx /rx data buffer or the tx data buffer is empty 10 pin irq is set to 1 if 12 bytes still are in the tx /rx data buffer or the tx data buffer is empty (default) 1 1 pin irq is set to 1 if the tx data buffer is empty table 9-3. control register 1 (function of bit 5) avcc_en function 0 (default) 1 enables avcc, if the ata5811/ ata5812 is in aux mode table 9-4. control register 1 (function of bit 4) fs function 0 433/868 mhz 1 315 mhz table 9-5. control register 1 (function of bit 2 and bit 1) opm1 opm0 function 0 0 idle mode (default) 0 1 tx mode 1 0 rx polling mode 11rx mode
36 4689f?rke?08/06 ata5811/ata5812 9.3.2 control register 2 (adr 1) 9.3.3 control register 3 (adr 2) table 9-6. control register 1 (function of bit 0) t_mode function 0 tx and rx function via tx/rx data buffer (default) 1 transparent mode, tx/rx data buffer disabled, tx modulation data stream via pin sdi_tmdi, rx modulation data stream via pin sdo_tmdo table 9-7. control register 2 (function of bit 7, bit 6, bit 5, bit 4, bit 3, bit 2 and bit 1) fr6 fr5 fr4 fr3 fr2 fr1 fr0 function 0000000freq2 = 0 0000001freq2 = 1 ....... 1011000freq2 = 88 (default) ....... 1111111freq2 = 127 note: tuning of f rf lsb?s (total 9 bits), frequency trimming, resolution of f rf is f xto /16384 which is approximately 800 hz (see ?xto? on page 23 , table 6-1 on page 25 ) table 9-8. control register 2 (function of bit 0 in rx mode) p_mode function (rx mode) 0 pin irq is set to 1 if the bi t-check is successful (default) 1 no effect on pin irq if the bit-check is successful table 9-9. control register 2 (function of bit 0 in tx mode) p_mode function (tx mode) 0 manchester modulator on (default) 1 manchester modulator off (nrz mode) table 9-10. control register 3 (function of bit 3 and bit 2) fr8 fr7 function 00freq3 = 0 0 1 freq3 = 128 1 0 freq3 = 256 (default) 1 1 freq3 = 384 note: tuning of f rf msb?s
37 4689f?rke?08/06 ata5811/ata5812 9.3.4 control register 4 (adr 3) table 9-11. control register 3 (function of bit 1) vsout_en function 0 output voltage power supply for external devices off (pin vsout) 1 output voltage power supply for external devices on (default) note: this bit is set to 1 if the bit-check is ok (rx_po lling, rx mode), an event at pin t1, t2, t3, t4 or t5 occurs or the bit power_on in the status register is 1. setting vsout_en = 0 in aux mode is not allowed table 9-12. control register 3 (function of bit 0) clk_on function 0 clock output off (pin clk) 1 clock output on (default) note: this bit is set to 1 if the bit-check is ok (rx_po lling, rx mode), an event at pin t1, t2, t3, t4 or t5 occurs or the bit power_on in the status register is 1. table 9-13. control register 4 (function of bit 7) ask_nfsk function 0 fsk mode (default) 1 ask mode table 9-14. control register 4 (function of bit 6, bit 5, bit 4, bit 3 and bit 2) sleep4 sleep3 sleep2 sleep1 sleep0 function sleep (t sleep = sleep 1024 t dclk x sleep ) 00000 0 00001 1 ..... 01010 10 (t sleep = 10 1024 t dclk x sleep ) (default) ..... 11111 31 table 9-15. control register 4 (function of bit 1) xsleep function 0x sleep = 1; extended t sleep off (default) 1x sleep = 8; extended t sleep on table 9-16. control register 4 (function of bit 0) xlim function 0x lim = 1; extended tlim_min, tlim_max off (default) 1x lim = 2; extended t lim_min , t lim_max on
38 4689f?rke?08/06 ata5811/ata5812 9.3.5 control register 5 (adr 4) table 9-17. control register 5 (function of bit 7 and bit 6) bitchk1 bitchk0 function 00n bit-check = 0 (0 bits checked during bit-check) 01n bit-check = 3 (3 bits checked during bit-check (default)) 10n bit-check = 6 (6 bits checked during bit-check) 11n bit-check = 9 (9 bits checked during bit-check) table 9-18. control register 5 (function of bit 5, bit 4, bit 3, bit 2, bit 1 and bit 0 in rx mode) lim_min5 lim_min4 lim_min3 lim_min2 lim_min1 lim_min0 function (rx mode) lim_min (lim_min < 10 are not applicable) (t lim_min = lim_min t xdclk ) 001010 10 001011 11 ...... 010000 16 (t lim_min = 16 t xdclk ) (default) ...... 111111 63 table 9-19. control register 5 (function of bit 5, bit 4, bit 3, bit 2, bit 1 and bit 0 in tx mode) lim_min5 lim_min4 lim_min3 lim_min2 lim_min1 lim_min0 function (tx mode) lim_min (lim_min < 10 are not applicable) (tx_bitrate = 1/((lim_min + 1) t xdclk 2) 001010 10 001011 11 ...... 010000 16 (tx_bitrate = 1/((16 + 1) t xdclk 2) (default) ...... 111111 63
39 4689f?rke?08/06 ata5811/ata5812 9.3.6 control register 6 (adr 5) 9.3.7 status register the status register indicates the current status of the transceiver and is readable via the 4-wire serial interface. setting power_on or p_on_aux or an event on st1, st2, st3, st4 or st5 is indicated by an irq. reading the status register resets the bits power_on, low_batt, p_on_aux and the irq table 9-20. control register 6 (function of bit 7 and bit 6) baud1 baud0 function 00 bit-rate range 0 (b0) 1.0 kbit/s to 2.5 kbit/s; t xdclk = 8 t dclk x lim 01 bit-rate range 1 (b1) 2.0 kbit/s to 5.0 kbit/s; t xdclk = 4 t dclk x lim 10 bit-rate range 2 (b2) 4.0 kbit/s to 10.0 kbit/s; t xdclk = 2 t dclk x lim ; (default) 11 bit-rate range 3 (b3) 8.0 kbit/s to 20.0 kbit/s; t xdclk = 1 t dclk x lim , note that the receiver is not working with >10 kb it/s in ask mode table 9-21. control register 6 (function of bit 5, bit 4, bit 3, bit 2, bit 1 and bit 0) lim_max5 lim_max4 lim_max3 lim_max2 lim_max1 lim_max0 function lim_max (lim_max < 12 are not applicable) (t lim_max = (lim_max ? 1) t xdclk ) 001100 12 001101 13 ...... 011100 28 (t lim_max = (28 ? 1) t xdclk ) (default) ...... 111111 63
40 4689f?rke?08/06 ata5811/ata5812 9.3.8 status register (adr 8) table 9-22. status register status bit function st5 status of pin t5 pin t5 = 0 st5 = 1 pin t5 = 1 st5 = 0 (see figure 9-3 on page 42 ) st4 status of pin t4 pin t4 = 0 st4 = 1 pin t4 = 1 st4 = 0 (see figure 9-3 on page 42 ) st3 status of pin t3 pin t3 = 0 st3 = 1 pin t3 = 1 st3 = 0 (see figure 9-3 on page 42 ) st2 status of pin t2 pin t2 = 0 st2 = 1 pin t2 = 1 st2 = 0 (see figure 9-3 on page 42 ) st1 status of pin t1 pin t1 = 0 st1 = 1 pin t1 = 1 st1 = 0 (see figure 9-3 on page 42 ) power_on indicates that the transceiver was woken up by pin pwr_on (rising edge on pin pwr_on). during power_on = 1, the bi ts vsout_en and clk_on in control register 3 are set to 1. (see figure 9-4 on page 43 ) low_batt indicates that output voltage on pin vsout is too low (v vsout < 2.38v typically) (see figure 9-5 on page 44 ) p_on_aux indicates that the auxiliary supply voltage on pin vaux is high enough to operate. state transition: a) off mode aux mode (see figure 7-2 on page 29 ) b) idle mode (vsout = vs1) idle mode (vsout = v_reg2) (see figure 9-6 on page 45 )
41 4689f?rke?08/06 ata5811/ata5812 9.4 pin tn to switch the transceiver from off to idle mode, pin tn must set to 0 (maximum 0.2 v vs2 ) for at least t tn_irq (see figure 9-2 ). the transceiver recognize the negative edge, sets pin n_reset to low and switches on dvcc, av cc and the power supply for external devices vsout. if v dvcc exceeds 1.5v (typically) and the xto is settled, the digital control logic is active and sets the status bit stn to 1 and an interrupt is issued (t tn_irq ). after the voltage on pin vsout exceeds 2.3v (typically) and the start-up time of the xto is elapsed the output clock on pin clk is available. because the enabling of pin clk is asynchro- nous the first clock cycle may be incomplete. n_reset is set to high if v vsout exceeds 2.38v (typically) and th e xto is settled. figure 9-2. timing pin tn, status bit stn stn (status register) irq clk n_reset dvcc, avcc vsout tn idle mode off mode v thres_2 = 2.38v (typ) v thres_1 = 2.3v (typ) t tn_irq 1.5v (typ)
42 4689f?rke?08/06 ata5811/ata5812 if the transceiver is in any ac tive mode (idle, aux, tx, rx, rx_polling), an in tegrated debounce logic is active. if there is an event on pin tn a debounce counter is set to 0 (t = 0) and started. the status is updated, an interrupt is issued and the debounce counter is stopped after reaching the counter value t = 8195 t dclk . an event on the same key input before reaching t = 8195 t dclk stops the debounce counter. an event on an other key input before reaching t = 8195 t dclk resets and restarts the debounce counter. while the debounce counter is running, the bits vsout_en and clk_on in control register 3 are set to 1. the interrupt is deleted after reading the status register or executes the command delete_irq. if a pin tn is not used, it can be left open because of an internal pull-up resistor (typically 50 k ? ). figure 9-3. timing flow pin tn, status bit stn idle mode or aux mode or tx mode or rx polling mode or rx mode stop debounce counter stn = 1 irq = 1 stop debounce counter stn = 0 irq = 1 stop debounce counter tn = stn ? pin tn = 0 ? t = 0 start debounce counter event on pin tn ? event on pin tn ? n n n n y y y y y n t = 8195 t ?
43 4689f?rke?08/06 ata5811/ata5812 9.5 pin pwr_on to switch the transceiver from off to idle mode, pin pwr_on must set to 1 (minimum 0.8 v vs2 ) for at least t pwr_on (see figure 9-4 ). the transceiver recognize the positive edge, sets pin n_reset to low and switches on dvcc, av cc and the power supply for external devices vsout. if v dvcc exceeds 1.5 v (typically) and the xto is sett led, the digital control logic is active and sets the status bit power_on to 1 and an interrupt is issued (t pwr_on_irq_1 ). after the voltage on pin vsout exceeds 2.3 v (typically) and the start-up time of the xto is elapsed the output clock on pin clk is available. because the enabling of pin clk is asynchro- nous the first clock cycle may be inco mplete. n_reset is set to high if v vsout exceeds 2.38 v (typically) and th e xto is settled. if the transceiver is in any active mode (idle, aux, rx, rx_polling, tx), a positive edge on pin pwr_on sets power_on to 1 (after t pwr_on_irq_2 ). the state transition power_on 0 1 gen- erates an interrupt. if power_on is still 1 during the positive edge on pin pwr_on no interrupt is issued. power_on and the interrupt is deleted after reading the status register. during power_on = 1, the bits vsout_en and clk_on in control register 3 are set to 1. note: it is not possible to set the transceiver to off mode by setting pin pw r_on to 0. if pin pwr_on is not used, it must be connected to gnd. figure 9-4. timing pin pwr_on, status bit power_on power_on (status register) irq clk n_reset dvcc, avcc vsout pwr_on off mode idle mode idle, aux, rx, rx polling, tx mode t pwr_on > t pwr_on_irq_2 t pwr_on > t pwr_on_irq_1 t pwr_on_irq_2 t pwr_on_irq_1 1.5v (typ) v thres_2 = 2.38v (typ) v thres_1 = 2.3v (typ)
44 4689f?rke?08/06 ata5811/ata5812 9.6 low battery indicator the status bit low_batt is set to 1 if the voltage on pin vsout v vsout drops under 2.38v (typically). low_batt is set to 0 if v vsout exceeds v thres_2 and the status register is read via the 4-wire serial interface (see figure 7-3 on page 31 ). figure 9-5. timing status bit low_batt idle, aux, tx, rx or rx polling mode read status register v vsout < 2.38v (typ) ? yes no low_batt = 1
45 4689f?rke?08/06 ata5811/ata5812 9.7 pin vaux to switch the transceiver from off to aux mode, the voltage on pin vaux v vaux must exceed 3.5v (typically) (see figure 9-6 ). if v vaux exceeds 2v (typically) pi n n_reset is set to low, dvcc and the power supply for exte rnal devices vsout are switched on. if v vaux exceeds 3.5v (typically) the status bit p_on_a ux is set to 1 and an interrupt is issued. after the voltage on pin vsout exceeds 2.3 v (typically) and the start-up time of the xto is elapsed the output clock on pin clk is available. because the enabling of pin clk is asynchro- nous the first clock cycle may be incomplete. n_reset is set to high if v vsout exceeds 2.38v (typically) and th e xto is settled. if the transceiver is in any active mode (idle, tx, rx, rx_polling), a positive edge on pin vaux and v vaux > vs1 + 0.5v sets p_on_aux to 1. the state transition p_on_aux 0 1 generates an interrupt. if p_on_aux is still 1 during the positive edge on pin vaux no interrupt is issued. p_on_aux and the interrupt is deleted after reading the status register. figure 9-6. timing pin vaux, status bit p_on_aux p_on_aux (status register) irq clk n_reset dvcc vsout vaux off mode aux mode idle, tx, rx, rx polling mode 2.0v (typ) 3.5v (typ) v thres_2 = 2.38v (typ) v thres_1 = 2.3v (typ) v vaux > vs1 + 0.5v (typ) v vaux > vs1 + 0.5v (typ)
46 4689f?rke?08/06 ata5811/ata5812 10. transceiver configuration the configuration of the transceiver takes pl ace via a 4-wire serial interface (cs, sck, sdi_tmdi, sdo_tmdo) and is organized in 8-bit uni ts. the configuration is initiated with a 8-bit command. while shifting the command into pin sdi_tmdi, the number of bytes in the tx/rx data buffer are available on pin sdo_tmdo. the read and write commands are followed by one or more 8-bit data units. each 8-bit data transmission begins with the msb. the serial interface is in reset state if the level on pin cs = low. 10.1 command: read tx/rx data buffer during a rx operation the user can read the received bytes in the tx/rx data buffer successively. figure 10-1. read tx/rx data buffer 10.2 command: write tx/rx data buffer during a tx operation the user can write the bytes in the tx/rx data buffer successively. an echo of the command and the tx data bytes are provided for the microcontroller on pin sdo_tmdo. figure 10-2. write tx/rx data buffer sck cs sdo_tmdo sdi_tmdi rx data byte 2 rx data byte 1 nr. bytes in the tx/rx data buffer command: read tx/rx data buffer x msb msb lsb lsb lsb msb x sck cs sdo_tmdo sdi_tmdi tx data byte 1 write tx/rx data buffer nr. bytes in the tx/rx data buffer command: write tx/rx data buffer tx data byte 1 msb msb lsb lsb lsb msb tx data byte 2
47 4689f?rke?08/06 ata5811/ata5812 10.3 command: read cont rol/status register the control and status registers can be read individually or successively. figure 10-3. read control/status register 10.4 command: write control register the control registers can be written individually or successively. an echo of the command and the data bytes are provided for the microcontroller on pin sdo_tmdo. figure 10-4. write control register 10.5 command: off command if avcc_en in control register 1 is 0, the input level on pin pwr_on is low and on the key inputs tn is high, the off command sets the transceiver in the off mode. figure 10-5. off command sck cs sdo_tmdo sdi_tmdi data c/s register x data c/s register y nr. bytes in the tx/rx data buffer command: read c/s register x msb msb lsb lsb lsb msb command: read c/s register z command: read c/s register y sck cs sdo_tmdo sdi_tmdi write control register x data control register x nr. bytes in the tx/rx data buffer command: write control register x msb msb lsb lsb lsb msb command: write control register y data control register x sck cs sdo_tmdo sdi_tmdi nr. bytes in the tx/rx data buffer command: off command lsb msb
48 4689f?rke?08/06 ata5811/ata5812 10.6 command: delete irq the delete irq command sets pin irq to low. figure 10-6. delete irq 10.7 command structure the three most significant bits of the command (bit 5 to bit 7) indicates the command type. bit 0 to bit 4 describes the target address when reading or writing a control or status register. in all other commands bit 0 to bit 4 have no effect and should be set to 0 for compatibility reasons with future products. 10.8 4-wire serial interface the 4-wire serial interface consists of the chip select (cs), the serial clock (sck), the serial data input (sdi_tmdi) and the serial data output (sdo_tmdo). data is transmitted/received bit by bit in synchronization with the serial clock. note: if the output level on pin n_reset is low, no data communication wit h the microcontroller is possible. when cs is low and the transparent mode is inactive (t_mode = 0), sdo_tmdo is in a high-impedance state. when cs is low and the transparent mode is active (t_mode = 1), the rx data stream is available on pin sdo_tmdo. sck cs sdo_tmdo sdi_tmdi nr. bytes in the tx/rx data buffer command: delete irq lsb msb table 10-1. command structure command msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read tx/rx data buffer 0 0 0 x x x x x write tx/rx data buffer 0 0 1 x x x x x read control/status register 0 1 0 a4 a3 a2 a1 a0 write control register 0 1 1 a4 a3 a2 a1 a0 off command 1 0 0xxxxx delete irq 1 0 1 x x x x x not used 1 1 0xxxxx not used 1 1 1xxxxx
49 4689f?rke?08/06 ata5811/ata5812 figure 10-7. serial timing 11. operation modes 11.1 rx operation the transceiver is set to rx operation with the bits opm0 and opm1 in control register 1 the transceiver is designed to consume less than 1 ma in rx operation while being sensitive to signals from a corresponding transmitter. this is achieved via the polling circuit. this circuits enables the signal path periodically for a short time. during this ti me the bit-check logic verifies the presence of a valid transmitter signal. only if a valid signal is detected the transceiver remains active and transfers the data to the connected microcontroller. this transfer take place either via the tx/rx data buffer or via the pin sdo_tmdo. if there is no valid signal present the transceiver is in sleep mode most of the time resulting in low cu rrent consumption. this condition is called rx polling mode. a c onnected microcontrolle r can be disabled during this time. all relevant parameters of the polling logic can be configured by the connected microcontroller. this flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate etc. in rx mode the rf transceiver is enabled perma nently and the bit-check logic verifies the pres- ence of a valid transmitter signal. if a valid signal is detected the transceiver transfers the data to the connected microcontroller. this transfer take place either via the tx/rx data buffer or via the pin sdo_tmdo. msb msb-1 lsb msb msb-1 x x x x x x cs sck sdo_tmdo sdi_tmdi t cs_disable t sck_setup2 t sck_hold t sck_setup1 t cycle x can be either v ii or v ih t cs_setup t out_enable t out_delay t setup t hold t out_disable table 11-1. control register 1 opm1 opm0 function 1 0 rx polling mode 11 rx mode
50 4689f?rke?08/06 ata5811/ata5812 11.1.1 rx polling mode if the transceiver is in rx pollin g mode it stays in a continuous cycle of three di fferent modes. in sleep mode the rf transceiver is disabled for the time period t sleep while consuming low current of i s = i idle_x . during the start-up period, t startup_pll and t startup_sig_proc , all signal processing cir- cuits are enabled and settled. in the following bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. if no valid signal is present, the transceiver is set back to sleep mode after the period t bit-check . this period varies check by check as it is a sta- tistical process. an average value for t bit-check is given in the electrical characteristics. during t startup_pll the current consumption is i s = i rx_x . during t startup_sig_proc and t bit-check the current consumption is i s = i startup_sig_proc_x . the condition of the transceiver is indicated on pin rx_active (see figure 11-1 on page 51 and figure 11-2 on page 52 ). the average current consumption in rx polling mode i p is different in 1 battery application, 2 battery application or car application. to calculate i p the index x must be replaced by vs1, 2 in 1 battery application, vs2 in 2 battery application or vs2, vaux in car application (see section ?electrical characteris- tics: general? on page 63 ) to save current it is recommended clk and v vsout be disabled during rx polling mode. i p does not include the current of the microcontroller_interface i vsint and the current of an external device connected to pin vsout (e.g., microcontroller). if clk and/or vsout is enabled during rx polling mode the current consum ption is calculated as follows: during t sleep , t startup_pll and t startup_sig_proc the transceiver is not sensitive to a transmitter sig- nal. to guarantee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. the required length of the preburst t preburst depends on the polling parameters t sleep , t startup_pll , t startup_sig_proc and t bit-check . thus, t bit-check depends on the actual bit rate and the number of bits (n bit-check ) to be tested 11.1.2 sleep mode the length of period t sleep is defined by the 5-bit word sleep in control register 4, the extension factor x sleep defined by the bit xsleep in control register 4 and the bas ic clock cycle t dclk . it is calculated to be: in us and european applications, the maximum value of t sleep is about 38 ms if x sleep is set to 1 (which is done by setting the bit xsleep in control register 4 to 0). the time resolution is about 1.2 ms in that case. the sleep time can be extended to about 300 ms by setting x sleep to 8 (which is done by setting xsleep in control register 4 to 1), the time resolution is then about 9.6 ms. 11.1.3 start-up mode during t startup_pll the pll is enabled and starts up. if the pll is locked, the signal processing circuit starts up (t startup_sig_proc ). after the start-up time all ci rcuits are in stable condition and ready to receive. i p i idle_x t sleep i startup_pll_x t startup_pll i rx_x t startup_sig_proc t bitcheck + () ++ t sleep t startup_pll t startup_sig_proc t bit_check ++ + ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- - = i s_poll i p i vsint i ext ++ = t preburst t sleep t startup_pll t startup_sig_proc t bit_check ++ + t sleep sleep 1024 t dclk x sleep =
51 4689f?rke?08/06 ata5811/ata5812 figure 11-1. flow chart polling mode/rx mode (t_mod e = 1, transparent mode inactive) start rx mode start rx polling mode start-up pll: the pll is enabled and locked. output level on pin rx_active ? high; i s = i startup_pll_x ; t startup_pll start-up signal processing: the signal processing circuit are enabled. output level on pin rx_active ? high; i s = i rx_x ; t startup_sig_proc the incomming data stream is analyzed. if the timing indicates a valid transmitter signal, the control bits vsout_en, clk_on and opm0 are set to 1 and the transceiver is set to receiving mode. otherwise it is set to sleep mode or to start_up mode. output level on pin rx_active ? high bit-check mode: sleep: defined by bits sleep 0 to sleep 4 in control register 4 798.5 t dclk (typ) t startup_pll : (br_range 0) is defined by the selected baud rate range and t dclk .the baud-rate range is defined by bit baud 0 and baud 1 in control register 6. if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. 882 t dclk (br_range 1) 498 t dclk (br_range 2) 306 t dclk (br_range 3) 210 t dclk t startup_sig_proc : defined by bit xsleep in control register 4 basic clock cycle t dclk : x sleep : depends on the result of the bit check. t bit-check : all circuits for analog signal processing are disabled. only xto and polling logic is enabled. output level on pin rx_active ? low; i s = i idle_x t sleep = sleep 1024 t dclk x sleep sleep mode: start-up mode: p_mode = 0 ? bit check ok ? set irq no yes yes yes yes no no no set vsout_en = 1 set clk_on = 1 set opm0 = 1 t sleep = 0 ? opm0 = 1 ? i s = i rx_x ; t bit-check the incomming data stream is passed via the tx/rx data buffer to the connected microcontroller. if an bit error occurs the transceiver is set back to start-up mode. output level on pin rx_active ? high receiving mode: bit error ? start bit detected ? yes yes no no rx data stream is written into the tx/rx data buffer i s = i rx_x if the bit check fails, the average time period for that check despends on the selected baud-rate range and on t xdclk . the baud-rate range is defined by bit baud 0 and baud 1 in control register 6. if the transceiver detects a bit errror after a successful bit check and before the start bit is detected pin irq will be set to high (only if p_mode = 0) and the transceiver is set back to start-up mode.
52 4689f?rke?08/06 ata5811/ata5812 figure 11-2. flow chart polling mode/rx mode (t_m ode = 1, transparent mode active) start rx mode start rx polling mode start-up pll: the pll is enabled and locked. output level on pin rx_active ? high; i s = i startup_pll_x ; t startup_pll start-up signal processing: the signal processing circuit are enabled. output level on pin rx_active ? high; i s = i rx_x ; t startup_sig_proc the incomming data stream is analyzed. if the timing indicates a valid transmitter signal, the control bits vsout_en, clk_on and opm0 are set to 1 and the transceiver is set to receiving mode. otherwise the transceiver is set to sleep mode (if opm0 = 0 and t sleep > 0) or stays in bit-check mode. output level on pin rx_active ? high bit-check mode: sleep: defined by bits sleep 0 to sleep 4 in control register 4 798.5 t dclk (typ) t startup_pll : (br_range 0) is defined by the selected baud rate range and t dclk .the baud-rate range is defined by bit baud 0 and baud 1 in control register 6. if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. 882 t dclk (br_range 1) 498 t dclk (br_range 2) 306 t dclk (br_range 3) 210 t dclk t startup_sig_proc : defined by bit xsleep in control register 4 basic clock cycle t dclk : x sleep : depends on the result of the bit check. t bit-check : all circuits for analog signal processing are disabled. only xto and polling logic is enabled. output level on pin rx_active ? low; i s = i idle_x t sleep = sleep 1024 t dclk x sleep sleep mode: start-up mode: bit check ok ? no yes yes yes no no set vsout_en = 1 set clk_on = 1 set opm0 = 1 t sleep = 0 ? opm0 = 1 ? i s = i rx_x ; t bit-check the incomming data stream is passed via pin sdo_tmdo to the connected microcontroller. if an bit error occurs the transceiver is not set back to start-up mode. output level on pin rx_active ? high receiving mode: level on pin cs = low ? yes no rx data stream available on pin sdo_tmdo i s = i rx_x if the bit check fails, the average time period for that check despends on the selected baud-rate range and on t xdclk . the baud-rate range is defined by bit baud 0 and baud 1 in control register 6. if in fsk mode the datastream is interrupted the fsk-demodulator-pll tends to lock out and is further not able to lock in, even there is a valid data stream available. in this case the transceiver must be set back to idle mode.
53 4689f?rke?08/06 ata5811/ata5812 11.1.4 bit-check mode in bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. this is done by subsequent time frame checks where the distance between 2 signal edges are continuously compared to a pro- grammable time window. the maximum count of th is edge to edge test before the transceiver switches to receiving mode is also programmable. 11.1.5 configuration the bit-check assuming a modulation scheme that contains 2 edg es per bit, two time frame checks are verify- ing one bit. this is valid for manchester, bi-phase and most other modulation schemes. the maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable n bit-check in control register 5. this implies 0, 6, 12 and 18 edge to edge checks respectively. if n bit-check is set to a higher value, the transceiver is less likely to switch to receiving mode due to noise. in the presence of a valid transmitter signal , the bit-check takes less time if n bit-check is set to a lower value. in rx polling mode, the bit-check time is not dependent on n bit-check . figure 11-3 shows an example where 3 bits are tested successful. figure 11-3. timing diagram for complete successful bit-check (number of checked bits: 3) according to figure 11-4 , the time window for the bit-check is defined by two separate time lim- its. if the edge to edge time t ee is in between the lower bit-check limit t lim_min and the upper bit-check limit t lim_max , the check will be continued. if t ee is smaller than limit t lim_min or exceeds t lim_max , the bit-check will be term inated and the transceive r switches to sleep mode. figure 11-4. valid time window for bit-check bit check mode bit check ok start-up mode receiving mode 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit rx_active demod_out bit check t startup_sig_proc t bit-check demod_out 1/f sig t ee t lim_min t lim_max
54 4689f?rke?08/06 ata5811/ata5812 for the best noise immunity it is recommended to use a low span between t lim_min and t lim_max . this is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. a '11111...' or a '10101...' sequence in manchester or bi-phase is a good choice concerning that advice. a good compromise betw een sensitivity and susceptib ility to noise regarding the expected edge to edge time t ee is a time window of 38%, to get the maximum sensitivity the time window should be 50% and then n bit-check 6. using preburst patterns that contain various edge to edge time periods, the bit-check limits must be programmed according to the required span. the bit-check limits are determined by means of the formula below: t lim_min = lim_min t xdclk t lim_max = (lim_max ? 1) t xdclk lim_min is defined by the bits lim_mi n 0 to lim_min 5 in control register 5. lim_max is defined by the bits lim_max 0 to lim_max 5 in control register 6. using the above formulas, lim_min and lim_max can be determined according to the required t lim_min , t lim_max and t xdclk . the time resolution defining t lim_min and t lim_max is t xdclk . the minimum edge to edge time t ee is defined according to the section ?receiving mode?. the lower limit should be set to lim_min 10. the maximum value of the upper limit is lim_max = 63. figure 11-5 , figure 11-6 on page 55 , and figure 11-7 on page 55 illustrate the bit-check for the bit-check limits lim_min = 14 and lim_max = 24. the signal processing circ uits are enabled during t startup_pll and t startup_sig_proc . the output of the ask/fsk demodulator (demod_out) is undefined during that period. when the bit-check becomes active, the bit-check counter is clocked with the cycle t xdclk . figure 11-5 shows how the bit-check proceeds if the bit-check counter value cv_lim is within the limits defined by lim_min and lim_max at the occurrence of a signal edge. in figure 11-6 on page 55 the bit-check fails as the value cv_lim is lower than the limit lim_min. the bit-check also fails if cv_lim reaches li m_max. this is illustrated in figure 11-7 on page 55 . figure 11-5. timing diagram during bit-check bit check ok bit check ok bit check mode start-up mode 1/2 bit 1/2 bit 1/2 bit rx_active (lim_min = 14, lim_max = 24) demod_out bit-check counter bit check t startup_sig_proc t bit-check t xdclk 1 234567812345678910111213141516171812345678910 11 0 12 13 14 15 1 2 3 4 5 67
55 4689f?rke?08/06 ata5811/ata5812 figure 11-6. timing diagram for failed bit-check (condition cv_lim < lim_min) figure 11-7. timing diagram for failed bit-check (condition: cv_lim lim_max) 11.1.6 duration of the bit-check if no transmitter is pr esent during the bit-chec k, the output of the ask/fsk demodulator delivers random signals. the bit-check is a statistical process and t bit-check varies for each check. there- fore, an average value for t bit-check is given in the electrical characteristics. t bit-check depends on the selected bit rate range and on t xdclk . a higher bit-rate range causes a lower value for t bit-check resulting in a lower current consumption in rx polling mode. in the presence of a valid transmitter signal, t bit-check is dependent on the frequency of that sig- nal, f sig , and the count of the bits, n bit-check . a higher value for n bit-check thereby results in a longer period for t bit-check requiring a higher value for the transmitter preburst t preburst . start-up mode t sleep t bit_check t startup_sig_proc bit check mode sleep mode 1/2 bit rx_active demod_out bit-check counter bit check (lim_min = 14, lim_max = 24) bit check failed (cv_lim < lim_min) 1 2345678123456789101112 0 0 start-up mode t sleep t bit_check t startup_sig_proc bit check mode sleep mode 1/2 bit rx_active demod_out bit-check counter bit check (lim_min = 14, lim_max = 24) bit check failed (cv_lim < lim_min) 1 2345678123456789101112 0 0 13 14 15 16 17 18 19 20 21 22 23 24
56 4689f?rke?08/06 ata5811/ata5812 11.1.7 receiving mode if the bit-check was successful for all bits specified by n bit-check , the transceiver switches to receiving mode. to activate a connected microcontroller, the bits vsout_en and clk_on in control register 3 are set to 1. an interrupt is issued at pin irq if the control bits t_mode = 0 and p_mode = 0. if the transparent mode is active (t_mode = 1) and the level on pin cs is low (no data transfer via the serial interface), the rx data stream is available on pin sdo_tmdo ( figure 11-8 ). figure 11-8. receiving mode (tmode = 1) if the transparent mode is inactive (t_mode = 0), the received data stream is buffered in the tx/rx data buffer (see figure 11-9 on page 57 ). the tx/rx data buffer is only usable for manchester and bi-phase coded signals. it is perm anently possible to transfer the data from the data buffer via the 4-wire serial interface to a microcontroller (see figure 10-1 on page 46 ). buffering of the data stream: after a successful bit-check, the transceiver s witches from bit-check mode to receiving mode. in receiving mode the tx/rx data buffer control logic is active and examines the incoming data stream. this is done, like in the bit-check, by subsequent time frame checks where the distance between two edges is continuous ly compared to a programmable time window as illustrated in figure 11-9 on page 57 , only two distances between two edges in manchester and bi-phase coded signals are valid (t and 2t). the limits for t are the same as used for the bit-check. they can be programmed in control register 5 and 6 (lim_min, lim_max). the limits for 2t are calculated as follows: lower limit of 2t: upper limit of 2t: if the result of lim_min_2t or lim_max_2t is not an integer value, it will be round up. sdo_tmdo demod_out bit check ok preburst byte 2 byte 1 start bit '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0' bit-check mode receiving mode byte 3 lim_min_2t lim_min lim_max + () lim_max lim_min ? () 2 ? ? = t lim_min_2t lim_min_2t t xdclk = lim_max_2t lim_min lim_max + () lim_max lim_min ? () 2 ? + = t lim_max_2t lim_max_2t - 1 () t xdclk =
57 4689f?rke?08/06 ata5811/ata5812 if the tx/rx data buffer control logic detects the start bit, the data stream is written in the tx/rx data buffer byte by byte. the start bit is part of the first data byte and must be different from the bits of the preburst. if the preburst consists of a sequence of '00000...', the start bit must be a 1. if the preburst consists of a sequence of '11111...', the start bit must be a 0. if the data stream consists of more than 16 bytes, a buffer overflow occurs and the tx/rx data buffer control logic overwrites the bytes already stored in the tx/rx data buffer. so it is very important to ensure that the data is read in time so that no buffer overflow occurs in that case (see figure 10-1 on page 46 ). there is a counter that indicates the number of received bytes in the tx/rx data buffer (see section ?transceiver configuration?). if a byte is transferred to the microcontroller, the counter is decremented, if a byte is received, the counter is incremented. the counter value is available via the 4-wire serial interface. an interrupt is issued, if the counter while c ounting forwards reaches the value defined by the control bits ir0 and ir1 in control register 1. figure 11-9. receiving mode (tmode = 0) if the tx/rx data buffer control logic detects a bit error, an interrupt is issued and the transceiver is set back to the start-up mode (see figure 11-1 on page 51 , figure 11-2 on page 52 and figure 11-10 on page 58 ). bit error: a) t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim_max_2t b) logical error (no edge detected in the bit center) note: the byte consisting of the bit error will not be stored in the tx/rx data buffer. thus it is not avail- able via the 4-wire serial interface. writing the control register 1, 4, 5 or 6 during receiving mode resets the tx/rx data buffer con- trol logic and the counter which indicates the number of received bytes. if the bits opm0 and opm1 are still '1' after writing to a control regist er, the transceiver changes to the start-up mode (start-up signal processing). demod_out bit check ok preburst byte 2 lsb readable via 4-wire ser ial interface tx/rx data buff er msb byte 1 start bit t 2t '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '0' '0' '0' '0' '0' byte 14, byte 30, ... byte 13, byte 29, ... byte 10, byte 26, ... byte 9, byte 25, ... byte 8, byte 24, ... byte 3, byte 19, ... byte 1, byte 17, ... byte 2, byte 18, ... byte 4, byte 20, ... byte 5, byte 21, ... byte 6, byte 22, ... byte 7, byte 23, ... byte 11, byte 27, ... byte 12, byte 28, ... byte 16, byte 32, ... byte 15, byte 31, ... 11 1 1 10 0 1 11 0 0 00 0 0 '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0' bit-check mode receiving mode byte 3
58 4689f?rke?08/06 ata5811/ata5812 figure 11-10. bit error (tmode = 0) 11.1.8 recommended lim_min and li m_max for maximum sensitivity the sensitivity measurement in the section ?low-if receiver? in table 5-3 on page 11 and table 5-4 on page 11 have been done with the lim_min and lim_max values according to table 11-3 . these values are optimized for maximum sensitivit y. note that since these limits are optimized for sensitivity the number of checked bit n bit-check has to be at least 6 to prevent the circuit from waking up to a often in polling mode due to noise. demod_out bit check ok byte n-1 byte 1 byte n+1 preburst byte n start-up mode bit-check mode receiving mode receiving mode bit error table 11-2. rx modulation scheme mode ask/_nfsk t_mode rf in bit in tx/rx data buffer level on pin sd0_tmdo rx 0 0f fsk_l f fsk_h 1z 0f fsk_h f fsk_l 0z 1f fsk_h ?1 1f fsk_l ?0 1 0f ask off f ask on 1 z 0f ask on f ask off 0 z 1f ask on ? 1 1f ask off ? 0 table 11-3. recommended lim_min and lim_max values for different bit rates f rf (f xtal )/ mhz 1.0 kbit/s br_range_0/xlim = 1 2.4 kbit/s br_range_0/xlim = 0 5 kbit/s br_range_1/xlim = 0 10 kbit/s br_range_2/xlim = 0 20 kbit/s br_range_3/xlim = 0 315.0 (12.73193) lim_min = 13 (261 s) lim_max = 38 (744 s) lim_min = 12 (121 s) lim_max = 34 (332 s) lim_min = 11 (55 s) lim_max = 32 (156 s) lim_min = 11 (28 s) lim_max = 32 (78 s) lim_min = 11 (14 s) lim_max = 31 (38 s) 433.92 (13.25311) lim_min = 13 (251 s) lim_max = 38 (715 s) lim_min = 12 (116 s) lim_max = 34 (319 s) lim_min = 11 (53 s) lim_max = 32 (150 s) lim_min = 11 (27 s) lim_max = 32 (75 s) lim_min = 11 (13 s) lim_max = 32 (37 s) 868.3 (13.41191) lim_min = 13 (248 s) lim_max = 38 (706 s) lim_min = 12 (115 s) lim_max = 34 (315 s) lim_min = 11 (52 s) lim_max = 32 (148 s) lim_min = 11 (26 s) lim_max = 32 (74 s) lim_min = 11 (13 s) lim_max = 32 (37 s)
59 4689f?rke?08/06 ata5811/ata5812 11.2 tx operation the transceiver is set to tx operation by us ing the bits opm0 and opm1 in the control register 1. before activating tx mode, the tx parameters (bit rate, modulation scheme ... ) must be selected as illustrated in figure 11-11 on page 60 . the bit rate depends on baud0 and baud1 in control register 6, lim_min0 to lim_min5 in control register 5 and xlim in control register 4 (see section ?control register? on page 35 ). the modulation is selected with ask_/nfsk in control register 4. the fsk frequency deviation is fixed to about 16 khz. if p_mode is set to 1, the manchester modulator is disabled and pattern mode is active (nrz, see table 11-5 on page 62 ). after the transceiver is set to tx mode the start-up mode is active and the pll is enabled. if the pll is locked, the tx mode is active. if the transceiver is in start-up or tx mode, the tx/rx data buffer can be loaded via the 4-wire serial interface. after the first byte is in the buffer and the tx mode is active, the transceiver starts transmitting automatically (beginning with the msb). while transmitting it is permanently possible to load new data in the tx/rx data buffer. to prevent a buffer overflow or interruptions during transmitting the user must ensure that data is loaded at the same speed as it is transmitted. there is a counter that indicates the number of bytes to be transmitted (see section ?transceiver configuration? on page 46 ). if a byte is loaded, the counter is incremented, if a byte is transmit- ted, the counter is decremented. the counter value is available via the 4-wire serial interface. an irq is issued, if the counter while counting backwards reaches the value defined by the control bits ir0 and ir1 in control register 1. note: writing to the control register 1, 4, 5 or 6 dur ing tx mode, resets the tx/rx data buffer and the counter which indicates the number of bytes to be transmitted. if t_mode in control register 1 is set to 1, the transceiver is in tx transparent mode. in this mode the tx/rx data buffer is disabled and the tx data stream must be applied on pin sdi_tmdi. figure 11-11 on page 60 illustrates the flow chart of the tx transparent mode. table 11-4. control register 1 opm1 opm0 function 01tx mode
60 4689f?rke?08/06 ata5811/ata5812 figure 11-11. tx operation (t_mode = 0) write tx/rx data buffer (max. 16 - number of bytes still in the tx/rx data buffer) write tx/rx data buffer (max. 16 byte) baud1, baud0: lim_max0 to lim_max5: select baud rate range don't care write control register 6 lim_min0 to lim_min5: bit_ck0, bit_ck1: select the baud rate don't care write control register 5 set idle opm1, opm0: write control register 1 n y n y y n pin irq = 1 ? idle mode tx mode start-up mode (tx) idle mode command: delete_irq tx more data bytes ? fr7, fr8: vsout_en: clk_on: adjust f rf set vsout_en = 1 don't care write control register 3 fr0 to fr6: p_mode: adjust f rf enable or disable the manchester modulator write control register 2 ir1, ir0: avcc_en: fs: opm1, opm0: t_mode: select an event which activates an interrupt don't care select operation frequency set opm1 = 0 and opm0 = 1 set t_mode = 0 write control register 1 xlim: ask/_nfsk: sleep0 to sleep4: xsleep: select the baud rate select modulation don't care don't care write control register 4 pin irq = 1 ? t startup = 331.5 t dcl k
61 4689f?rke?08/06 ata5811/ata5812 figure 11-12. tx transparent mode (t_mode = 1) apply tx data on pin sdi_tmdi set idle (opm1 = 0, opm0 = 1 opm1, opm0: write control register 1 idle mode tx mode start-up mode (tx) idle mode fr7, fr8: vsout_en: clk_on: adjust f rf set vsout_en = 1 don't care write control register 3 fr0 to fr6: p_mode: adjust f rf don't care write control register 2 ir1, ir0: avcc_en: fs: opm1, opm0: t_mode: don't care don't care select operation frequency set opm1 = 0 and opm0 = 1 set t_mode = 1 write control register 1 xlim: ask/_nfsk: sleep0 to sleep4: xsleep: don't care select modulation don't care don't care write control register 4 t startup = 331.5 t dcl k
62 4689f?rke?08/06 ata5811/ata5812 11.3 interrupts via pin irq, the transceiver signals different operating conditions to a connected microcontrol- ler. if a specific operating condition occurs, pin irq is set to high level. if an interrupt occurs it is recommended to delete the interrupt be immediately deleted by reading the status register, thus the next possible interrupt doesn?t get lost. if the interrupt pin doesn?t switch to low level by read- ing the status register the interrupt was triggered by the rx/tx data buffer. in this case read or write the rx/tx data buffer according to table 11-6 . table 11-5. tx modulation schemes mode ask/_nfsk p_mode t_mode bit in tx/rx data buffer level on pin sdi_tmdi rf out tx 0 001xf fsk_l f fsk_h 000xf fsk_h f fsk_l 101x f fsk_h 100x f fsk_l x1x1 f fsk_h x1x0 f fsk_l 1 001xf ask off f ask on 000xf ask on f ask off 101x f ask on 100x f ask off x1x1 f ask on x1x0 f ask off table 11-6. interrupt handling operating conditions which sets pin irq to high level operations which sets pin irq to low level events in status register state transition of status bit stn (0 1; 1 0) read status register or command delete irq appearance of status bit power_on (0 1) appearance of status bit p_on_aux (0 1) events during tx operation (t_mode = 0) 4, 8 or 12 bytes are in the tx data buffer or the tx data buffer is empty (depends on ir0 and ir1 in control register 1). write tx data buffer or write control register 1 or write control register 4 or write control register 5 or write control register 6 or command delete irq events during rx operation (t_mode = 0) 4, 8 or 12 received bytes are in the rx data buffer or a receiving error is occurred (depends on ir0 and ir1 in control register 1). read rx data buffer (1) or write control register 1 or write control register 4 or write control register 5 or write control register 6 or command delete irq successful bit-check (p_mode = 0) note: 1. during reading of the rx/tx buffer, no irq is issued, due to the received bytes or a receiving error.
63 4689f?rke?08/06 ata5811/ata5812 12. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. max. unit junction temperature t j 150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +105 c supply voltage vs2 v maxvs2 ?0.3 +7.2 v supply voltage vs1 v maxvs1 ?0.3 +4 v supply voltage vaux v maxvaux ?0.3 +7.2 v supply voltage vsint v maxvsint ?0.3 +5.5 v esd (human body model esd s 5.1) every pin hbm ?2 +2 kv esd (machine model jedec a115a) every pin mm ?200 +200 v maximum input level, input matched to 50 ? p in_max 10 dbm 13. thermal resistance parameters symbol value unit junction ambient r thja 25 k/w 14. electrical charac teristics: general all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* 1 rx_tx_idle mode 1.1 rf operating frequency range ata5811 v 433_n868 =0 v 4, 10 f rf 867 870 mhz a ata5811 v 433_n868 =avcc 4, 10 f rf 433 435 mhz a ata5812 v 433_n868 =0 v 4, 10 f rf 313 316 mhz a 1.2 supply current off mode v vs1 =v vs2 =3 v, v vsint =0 v (1 battery) and v vs2 = 6 v (2 battery) off mode is not available if v vs2 =v vaux =5 v v vsint =0v (car) i s_off <10 na a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
64 4689f?rke?08/06 ata5811/ata5812 1.3 supply current idle mode v vsout disabled, xto running v vs1 = v vs2 = 3v (1 battery) i s_idle 220 a b v vs2 = 6v (2 battery) i s_idle 310 a b v vs2 = v vaux = 5v (car) i s_idle 310 a b 1.4 system start-up time from off mode to idle mode including reset and xto start-up (see figure 9-4 on page 43 ) xtal: c m = 5 ff, c 0 = 1.8 pf, r m = 15 ? t pwr_on_irq_1 0.3 ms c 1.5 rx start-up time from idle mode to receiving mode n bit-check = 3 bit rate = 20 kbit/s, br_range_3 (see figure 11-1 on page 51 , figure 11-2 on page 52 and figure 11-3 on page 53 ) t startup_pll + t startup_sig_proc + t bit-chek 1.39 ms a 1.6 tx start-up time from idle mode to tx mode (see figure 11-11 on page 60 ) t startup 0.4 ms a 2 receiver/rx mode 2.1 supply current rx mode f rf = 433.92 mhz and f rf = 315 mhz 17, 18 i s_rx 10.5 ma a f rf = 868 mhz 17, 18 i s_rx 10.3 ma a 2.2 supply current rx polling mode t sleep = 49.45 ms x sleep = 8, sleep = 5 bit rate = 20 kbit/s fsk, v vsout disabled 17, 18 i p 444 a b 2.3 input sensitivity fsk f rf = 433.92 mhz fsk deviation f dev = 16 khz limits according to table 11-3 on page 58 , ber = 10 -3 t amb = 25c bit rate 20 kbit/s (4) p ref_fsk ?104.0 ?106.0 ?107.5 dbm b bit rate 2.4 kbit/s (4) p ref_fsk ?107.5 ?109.5 ?111.0 dbm b 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
65 4689f?rke?08/06 ata5811/ata5812 2.4 input sensitivity ask f rf = 433.92 mhz ask 100%, level of carrier limits according to table 11-3 on page 58 , ber = 10 -3 t amb = 25c bit rate 10 kbit/s (4) p ref_ask ?110.5 ?112.5 ?114.0 dbm b bit rate 2.4 kbit/s (4) p ref_ask ?114.5 ?116.5 ?118.0 dbm b 2.5 sensitivity change at f rf = 315.0 mhz f rf = 868.3 mhz compared to f rf = 433.92 mhz f rf = 433.92 mhz to f rf = 315.00 mhz f rf = 433.92 mhz to f rf = 868.00 mhz p = p ref_ask + ? p ref1 + ? p ref2 p = p ref_fsk + ? p ref1 + ? p ref2 (4) ? p ref1 ?1.0 +2.7 db b 2.6 maximum frequency offset in fsk mode maximum frequency difference of f rf between receiver and transmitter in fsk mode (f rf is the center frequency of the fsk signal with f dev = 16 khz) (4) ? f offset ?58 +58 khz b 2.7 sensitivity change versus temperature, supply voltage and frequency offset fsk f dev = 16 khz ? f offset 58 khz ask 100% ? f offset 58 khz p = p ref_ask + ? p ref1 + ? p ref2 p = p ref_fsk + ? p ref1 + ? p ref2 (4) ? p ref2 +4.5 ?1.5 b 2.8 supported fsk frequency deviation with up to 2 db loss of sensitivity. note that the tolerable frequency offset is for f dev = 22 khz, 6 khz lower than for f dev = 16 khz hence ? f offset 52 khz (4) f dev 14 16 22 khz b 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
66 4689f?rke?08/06 ata5811/ata5812 2.9 system noise figure f rf = 315 mhz (4) nf 6.0 db b f rf = 433.92 mhz (4) nf 7.0 db b f rf = 868.3 mhz (4) nf 9.7 db b 2.10 intermediate frequency f rf = 868.3 mhz f if 226 khz a f rf = 433.92 mhz f if 223 khz a f rf = 315 mhz f if 227 khz a 2.11 system bandwidth this value is for information only! note that for crystal and system frequency offset calculations, ? f offset must be used. (4) sbw 185 khz a 2.12 system outband 2nd-order input intercept point with respect to f if ? f meas1 = 1,800 mhz ? f meas2 = 2,026 mhz f if = ? f meas2 ? ? f meas1 (4) iip2 +50 dbm c 2.13 system outband 3rd-order input intercept point ? f meas1 = 1.8 mhz ? f meas2 = 3.6 mhz f rf = 315 mhz (4) iip3 ?22 dbm c f rf = 433.92 mhz (4) iip3 ?21 dbm c f rf = 868.3 mhz (4) iip3 ?17 dbm c 2.14 system outband input 1 db compression point ? f meas1 = 10 mhz f rf = 315 mhz (4) i1dbcp ?31 dbm c f rf = 433.92 mhz (4) i1dbcp ?30 dbm c f rf = 868.3 mhz (4) i1dbcp ?27 dbm c 2.15 lna input impedance f rf = 315 mhz 4 z in_lna (44 ? j233) ? c f rf = 433.92 mhz 4 z in_lna (32 ? j169) ? c f rf = 868.3 mhz 4 z in_lna (21 ? j78) ? c 2.16 maximum peak rf input level, ask and fsk ber < 10 -3 , ask: 100% (4) p in_max ?10 +10 dbm c fsk: f dev = 16 khz (4) p in_max ?10 +10 dbm c 2.17 lo spurious at lna_in f < 1 ghz (4) ?57 dbm c f >1 ghz (4) ?47 dbm c f rf = 315 mhz (4) ?100 dbm c f rf = 433.92 mhz (4) ?97 dbm c f rf = 868.3 mhz (4) ?84 dbm c 2.18 image rejection within the complete image band (4) 20 30 db a 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
67 4689f?rke?08/06 ata5811/ata5812 2.19 useful signal to interferer ratio peak level of useful signal to peak level of interferer for ber < 10 -3 with any modulation scheme of interferer fsk br_ranges 0, 1, 2 (4) snr fsk0-2 23dbb fsk br_range_3 (4) snr fsk3 46dbb ask (p rf < p rfin_high )(4) snr ask 10 12 db b 2.20 rssi output dynamic range (4), 36 d rssi 70 db a lower level of range f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz (4), 36 p rfin_low ?116 ?115 ?112.3 dbm dbm dbm a upper level of range f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz (4), 36 p rfin_high ?46 ?45 ?42.3 dbm dbm dbm a gain (4), 36 5.5 8.0 10.5 mv/db a output voltage range (4), 36 ov rssi 400 1100 mv a 2.21 output resistance rssi pin rx mode tx mode 36 r rssi 8 32 10 40 12.5 50 k ? c 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
68 4689f?rke?08/06 ata5811/ata5812 2.22 blocking sensitivity (ber = 10 -3 ) is reduced by 6 db if a continuous wave blocking signal at ? f is ? p block higher than the useful signal level (bit rate = 20 kbit/s, fsk, f dev 16khz, manchester code) f rf = 315 mhz ? f 0.75 mhz ? f 1.0 mhz ? f 1.5 mhz ? f 5 mhz ? f 10 mhz (4) ? p block 56 60 63 69 71 dbc c f rf = 433.92 mhz ? f 0.75 mhz ? f 1.0 mhz ? f 1.5 mhz ? f 5 mhz ? f 10 mhz (4) ? p block 55 59 62 68 70 dbc c f rf = 868.3 mhz ? f 0.75 mhz ? f 1.0 mhz ? f 1.5 mhz ? f 5 mhz ? f 10 mhz (4) ? p block 50 53 57 67 69 dbc c 2.23 cdem c 6 in figure 2-1 on page 6 , figure 3-1 on page 7 and figure 4-1 on page 8 37 ?5% 15 +5% nf d 3 power amplifier/tx mode 3.1 supply current tx mode power amplifier off f rf = 868.3 mhz i s_tx_paoff 6.50 ma a f rf = 433.92 mhz and f rf = 315 mhz i s_tx_paoff 6.95 ma a 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
69 4689f?rke?08/06 ata5811/ata5812 3.2 output power 1 v vs1 = v vs2 = 3v t amb = 25c v pwr_h = 0v f rf = 315 mhz r r_pwr = 56 k ? r lopt = 2.5 k ? f rf = 433.92 mhz r r_pwr = 56 k ? r lopt = 2.3 k ? f rf = 868.3 mhz r r_pwr = 30 k ? r lopt = 1.3 k ? rf_out matched to r lopt // j/(2 f rf 1.0 pf ) (10) p ref1 ?2.5 0 +2.5 dbm b 3.3 supply current tx mode power amplifier on 1 pa on/0 dbm f rf = 315 mhz 17, 18 i s_tx_paon1 8.5 ma b f rf = 433.92 mhz 17, 18 i s_tx_paon1 8.6 ma b f rf = 868.3 mhz 17, 18 i s_tx_paon1 9.6 ma b 3.4 output power 2 v vs1 = v vs2 = 3v t amb = 25c v pwr_h = 0v f rf = 315 mhz r r_pwr = 30 k ? r lopt = 1.0 k ? f rf = 433.92 mhz r r_pwr = 27 k ? r lopt = 1.1 k ? f rf = 868.3 mhz r r_pwr = 16 k ? r lopt = 0.5 k ? rf_out matched to r lopt // j/(2 f rf 1.0 pf ) (10) p ref2 3.5 5.0 6.5 dbm b 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
70 4689f?rke?08/06 ata5811/ata5812 3.5 supply current tx mode power amplifier on 2 pa on/5 dbm f rf = 315 mhz 17, 18 i s_tx_paon2 10.3 ma b f rf = 433.92 mhz 17, 18 i s_tx_paon2 10.5 ma b f rf = 868.3 mhz 17, 18 i s_tx_paon2 11.2 ma b 3.6 output power 3 v vs1 = v vs2 = 3v t amb = 25c v pwr_h = avcc f rf = 315 mhz r r_pwr = 30 k ? r lopt = 0.38 k ? f rf = 433.92 mhz r r_pwr = 27 k ? r lopt = 0.36 k ? f rf = 868.3 mhz r r_pwr = 20 k ? r lopt = 0.22 k ? rf_out matched to r lopt // j/(2 f rf 1.0 pf ) (10) p ref3 8.5 10 11.5 dbm b 3.7 supply current tx mode power amplifier on 3 pa on/10dbm f rf = 315 mhz 17, 18 i s_tx_paon3 15.7 ma b f rf = 433.92 mhz 17, 18 i s_tx_paon3 15.8 ma b f rf = 868.3 mhz 17, 18 i s_tx_paon3 17.3 ma b 3.8 output power variation for full temperature and supply voltage range t amb = ?40c to +105c p out = p refx + ? p refx x = 1, 2 or 3 v vs1 = v vs2 = 3.0v (10) ? p ref ?0.8 ?1.5 db b v vs1 = v vs2 = 2.4v (10) ? p ref ?3.5 db b v vs1 = v vs2 = 2.7v (10) ? p ref ?2.5 db c 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
71 4689f?rke?08/06 ata5811/ata5812 3.9 impedance rf_out in rx mode f rf = 315 mhz 10 z rf_out_rx (36 ? j502) ? c f rf = 433.92 mhz 10 z rf_out_rx (19 ? j366) ? c f rf = 868.3 mhz 10 z rf_out_rx (2.8 ? j141) ? c 3.10 noise floor power amplifier at 10 mhz/at 5 dbm f rf = 868.3 mhz (10) l tx10m ?125 dbc/hz c at f rf = 433.92 mhz (10) l tx10m ?126 dbc/hz c f rf = 315 mhz (10) l tx10m ?127 dbc/hz c 3.11 ask modulation rate this correspond to 10 kbit/s manchester coding and 20 kbit/s nrz coding f data_ask 10 khz c 4xto 4.1 pulling xto due to xto, c l1 and c l2 tolerances pulling at nominal temperature and supply voltage f xtal = resonant frequency of the xtal c 0 1.5 pf r m 120 ? 24, 25 ? f xto1 a c m 7.0 ff c m 14 ff ?50 ?100 f xtal +50 +100 ppm 4.2 transconductance xto at start at start-up, after start-up the amplitude is regulated to v ppxtal 24, 25 g m, xto 19 ms b 4.3 xto start-up time c 0 2.2 pf c m = 4.0 ff to 7.0 ff r m 120 ? 24, 25 t pwr_on_irq_1 300 800 s a 4.4 maximum c 0 of xtal required for stable operation with internal load capacitors 24, 25 c 0max 3.8 pf d 4.5 internal capacitors c l1 and c l2 24, 25 c l1 , c l2 14.8 18 pf 21.2 pf b 4.6 pulling of radio frequency f rf due to xto, c l1 and c l2 versus temperature and supply changes 1.5 pf c 0 2.2 pf c m = 4.0 ff to 7.0 ff r m 120 ? pll adjusted with freq at nominal temperature and supply voltage 4, 10 ? f xto2 ?2 +2 ppm c 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
72 4689f?rke?08/06 ata5811/ata5812 4.7 amplitude xtal after start-up c m = 5 ff, c 0 = 1.8 pf r m = 15 ? v(xtal1, xtal2) peak-to-peak value 24, 25 v ppxtal 700 mvpp c v(xtal1) peak-to-peak value 24, 25 v ppxtal 350 mvpp c 4.8 maximum series resistance r m of xtal at start-up c 0 2.2 pf, start-up may take longer under these conditions 24, 25 z xtal12_start ?1,500 ?2,000 ? b 4.9 maximum series resistance r m of xtal after start-up c 0 2.2 pf c m = 4.0 ff to 7.0 ff r m 120 ? 24, 25 r m_max 15 120 ? b 4.10 nominal xtal load resonant frequency freq = 3,928 f rf = 868.3 mhz f rf = 433.92 mhz f rf = 315 mhz 24, 25 f xtal 13.41191 13.25311 12.73193 mhz mhz d 4.11 external clk frequency freq = 3,928 30 f clk mhz d f rf = 868.3 mhz clk division ratio = 3 clk has nominal 50% duty cycle 30 f clk 4.471 mhz d f rf = 433.92 mhz clk division ratio = 3 clk has nominal 50% duty cycle 30 f clk 4.418 mhz d f rf = 315 mhz clk division ratio = 3 clk has nominal 50% duty cycle 30 f clk 4.244 mhz d 4.12 dc voltage after start-up v dc (xtal1, xtal2) xto running (idle mode, rx mode and tx mode) 24, 25 v dcxto ?150 ?30 mv 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 . f clk f xto 3 ---------- - =
73 4689f?rke?08/06 ata5811/ata5812 5 synthesizer 5.1 spurious tx mode at f clk , clk enabled f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz sp tx ?72 ?68 ?70 dbc a at f xto f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz sp tx ?70 ?66 ?60 dbc a 5.2 spurious rx mode at f clk , clk enabled f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz sp rx < ?75 < ?75 < ?75 dbc a at f xto f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz sp rx ?75 ?75 ?68 dbc a 5.3 in loop phase noise tx mode measured at 20 khz distance to carrier f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz l tx20k ?85 ?80 ?75 dbc/hz a 5.4 phase noise at 1m rx mode f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz l rx1m ?121 ?120 ?113 dbc/hz a 5.5 phase noise at 1m tx mode f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz l tx1m ?113 ?111 ?107 dbc/hz a 5.6 phase noise at 10m rx mode noise floor pll l rx10m ?135 dbc/hz b 5.7 loop bandwidth pll tx mode frequency where the absolute value loop gain is equal to 1 f loop_pll 70 khz b 5.8 frequency deviation tx mode f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz f dev_tx 15.54 16.17 16.37 khz d 5.9 frequency resolution f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz 4, 10 ? f step_pll 777.1 808.9 818.6 hz d 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
74 4689f?rke?08/06 ata5811/ata5812 5.10 fsk modulation rate this correspond to 20 kbit/s manchester coding and 40 kbit/s nrz coding f data_fsk 20 khz b 6 rx/tx switch 6.1 impedance rx mode rx mode, pin 38 with short connection to gnd, f rf = 0hz (dc) 39 z switch_rx 23000 ? a f rf = 315 mhz 39 z switch_rx (11.3 ? j214) ? c f rf = 433.92 mhz 39 z switch_rx (10.3 ? j153) ? c f rf = 868.3 mhz 39 z switch_rx (8.9 ? j73) ? c 6.2 impedance tx mode tx mode, pin 38 with short connection to gnd, f rf = 0hz (dc) 39 z switch_tx 5 ? a f rf = 315 mhz f rf = 433.92 mhz f rf = 868.3 mhz 39 z switch_tx (4.8 + j3.2) (4.5 + j4.3) (5 + j9) ? c c c 7 microcontroller interface 7.1 voltage range for microcontroller interface i vsint < 10 a if clk is disabled and all interface pins are in stable condition and unloaded 27, 28, 29, 30, 31, 32, 33, 34, 35 2.4 5.25 v a 7.2 clk output rise and fall time f clk < 4.5 mhz c l = 10 pf c l = load capacitance on pin clk 2.4 v v vsint 5.25v 20% to 80% v vsint 30 t rise t fall 20 20 30 30 ns ns b 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 .
75 4689f?rke?08/06 ata5811/ata5812 7.4 current consumption of the microcontroller interface clk enabled v vsout enabled clk disabled v vsout enabled v vsout disabled c l = load capacitance on pin clk (all interface pins, except pin clk, are in stable condition and unloaded) 27 i vsint < 10 a < 10 a 7.5 internal equivalent capacitance used for current calculation 30, 27 cclk 8 pf b 8 power supply general definitions and aux mode 8.1 current consumption of an external device connected to pin vsout i ext i ext = i vsout ? i vsint i ext = i vsout 8.2 aux mode 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 . i vsint c clk c l + () v vsint f xto 3 --------------------------------------------------------------------------- - = vsint vsout i vsout i ext i vsint vsint vsout i vsint i ext = i vsout vaux i aux_vaux
76 4689f?rke?08/06 ata5811/ata5812 8.3 power supply output voltage aux mode v vaux 4v i vsout 13.5 ma (3.25v regulator mode, v_reg2, see figure 7-1 on page 27 ) 22 v vsout 2.7 3.5 v a 8.4 current in aux mode on pin vaux i vsout = 0 v vaux = 6v v vaux = 4v to 7v 19 i aux_vaux 380 500 500 a a b 8.5 supply current aux mode clk enabled v vsout enabled clk disabled v vsout enabled 19, 22, 27 i s_aux i s_aux = i aux_vaux + i vsint + i ext i s_aux = i aux_vaux + i ext 8.6 supported voltage range vaux 19 v vaux 467v 14. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v (1-battery application), v vs2 = 4.4v to 6.6v (2-battery application) and v vs2 = v vaux = 4.75v to 5.25v (car application). typical values are given at v vs1 = v vs2 = 3v and t amb = 25c, f rf = 433.92 mhz (1-battery application) unless otherwise specifie d. details about current consumption, timing and digital pin properties can be found in the specific se ctions of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 ? according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 and rf_out matched to 50 ? according to figure 5-10 on page 19 with component values according to table 5-7 on page 20 . 15. electrical characterist ic: 1-battery application all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v typical values at v vs1 =v vs2 = 3v and t amb = 25c. application according to figure 2-1 on page 6 . f rf = 315.0 mhz/433.92 mhz/868.3 mh z unless otherwise specified no. parameters test conditions pin symbol min. typ. max. unit type* 9 1-battery application 9.1 supported voltage range (every mode except high power tx mode) 1-battery application pwr_h = gnd 17, 18 v vs1 , v vs2 2.4 3.6 v a 9.2 supported voltage range (high power tx mode) 1-battery application pwr_h = avcc 17, 18 v vs1 , v vs2 2.7 3.6 v a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. the voltage of vaux may rise up to 2v. the current i vaux may not exceed 100 a. i idle_vs1,2 or i rx_vs1,2 or i startup_pll_vs1,2 or i tx_vs1,2 vs1 vs2
77 4689f?rke?08/06 ata5811/ata5812 9.3 power supply output voltage 1-battery application v vs1 = v vs2 2.6v vaux open (1) i vsout 13.5 ma (no voltage regulator to stabilize v vsout ) v vs1 = v vs2 2.425v vaux open (1) i vsout 1.5 ma (no voltage regulator to stabilize v vsout ) 22 v vsout 2.4 v vs1 vb 9.4 supply voltage for microcontroller interface 27 v vsint 2.4 5.25 v a 9.5 threshold hysteresis v thres_2 ? v thres_1 22 ? v thres 60 80 100 mv b 9.6 reset threshold voltage at pin vsout (n_reset) 22 v thres_1 2.18 2.3 2.42 v a 9.7 reset threshold voltage at pin vsout (low_batt) 22 v thres_2 2.26 2.38 2.5 v a 9.8 supply current off mode v vs1 = v vs2 3.6v v vsint = 0v 17, 18, 22, 27 i s_off 2 350 na a 9.9 current in idle mode on pin vs1 and vs2 v vs1 = v vs2 3v i vsout = 0 clk enabled v vsout enabled clk disabled v vsout enabled v vsout disabled 17, 18 i idle_vs1, 2 312 260 225 430 370 320 a a a a b b 9.10 supply current idle mode 17, 18, 22, 27 i s_idle i s_idle = i idle_vs1, 2 + i vsint + i ext 9.11 current in rx mode on pin vs1and vs2 v vs1 = v vs2 3v i vsout = 0 17, 18 i rx_vs1, 2 10.5 14 ma a 9.12 supply current rx mode clk enabled v vsout enabled 17, 18, 22, 27 i s_rx i s_rx = i rx_vs1, 2 + i vsint + i ext 9.13 current during t startup_pll on pin vs1 and vs2 v vs1 = v vs2 3v i vsout = 0 17, 18 i startup_pll_vs1, 2 8.8 11.5 ma c 15. electrical characteristic: 1- battery application (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v typical values at v vs1 =v vs2 = 3v and t amb = 25c. application according to figure 2-1 on page 6 . f rf = 315.0 mhz/433.92 mhz/868.3 mh z unless otherwise specified no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. the voltage of vaux may rise up to 2v. the current i vaux may not exceed 100 a.
78 4689f?rke?08/06 ata5811/ata5812 9.14 current in rx polling mode on pin vs1 and vs2 9.15 supply current rx polling mode clk enabled v vsout enabled clk disabled v vsout enabled v vsout disabled 17, 18, 22, 27 i s_poll i s_poll = i p + i vsint + i ext i s_poll = i p + i ext i s_poll = i p 9.16 current in tx mode on pin vs1 and vs2 v vs1 = v vs2 3v i vsout = 0 pout = 5 dbm/10 dbm 315 mhz/5 dbm 315 mhz/10 dbm 433.92 mhz/5 dbm 433.92 mhz/10 dbm 868.3 mhz/5 dbm 868.3 mhz/10 dbm 17, 18 i tx_vs1_vs2 10.3 15.7 10.5 15.8 11.2 17.3 13.4 20.5 13.5 20.5 14.5 22.5 ma b 9.17 supply current tx mode clk enabled v vsout enabled clk disabled v vsout enabled 17, 18, 22, 27 i s_tx i s_tx = i tx_vs1, 2 + i vsint + i ext i s_tx = i tx_vs1, 2 + i ext 15. electrical characteristic: 1- battery application (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.4v to 3.6v typical values at v vs1 =v vs2 = 3v and t amb = 25c. application according to figure 2-1 on page 6 . f rf = 315.0 mhz/433.92 mhz/868.3 mh z unless otherwise specified no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. the voltage of vaux may rise up to 2v. the current i vaux may not exceed 100 a. i p i idle_vs1,2 t sleep i startup_pll_vs1,2 t startup_pll i rx_vs1,2 t startup_sig_proc t bitcheck + () + + t sleep t startup_pll t startup_sig_proc t bitcheck ++ + ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------- - =
79 4689f?rke?08/06 ata5811/ata5812 16. electrical characteristic s: 2-battery application all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs2 = 4.4v to 6.6v typical values at v vs2 = 6v and t amb = 25c. application according to figure 4-1 on page 8 . f rf = 315.0 mhz/433.92 mhz/868.3 mhz unless otherwise specified no. parameters test conditions pin symbol min. typ. max. unit type* 10 2-battery application 10.1 supported voltage range 2-battery application 17 v vs2 4.4 6.6 v a 10.2 power supply output voltage 2 battery application v vs2 4.4v vaux open (1) i vsout 13.5 ma (3.3v regulator mode, v_reg1, see figure 7-1 on page 27 ) 22 v vsout 3.0 3.5 v a 10.3 supply voltage for microcontroller interface 27 v vsint 2.4 5.25 v a 10.4 threshold hysteresis v thres_2 ? v thres_1 22 ? v thres 60 80 100 mv b 10.5 reset threshold voltage at pin vsout (n_reset) 22 v thres_1 2.18 2.3 2.42 v a 10.6 reset threshold voltage at pin vsout (low_batt) 22 v thres_2 2.26 2.38 2.5 v a 10.7 supply current off mode v vs2 6.6v v vsint = 0v 17, 22, 27 i s_off 10 350 na a 10.8 current in idle mode on pin vs2 v vs2 6v i vsout = 0 clk enabled v vsout enabled clk disabled v vsout enabled v vsout disabled 17 i idle_vs2 410 348 309 560 490 430 a a a a b b 10.9 supply current idle mode 17, 22, 27 i s_idle i s_idle = i idle_vs2 + i vsint + i ext 10.10 current in rx mode on pin vs2 i vsout = 0 17 i rx_vs2 10.8 14.5 ma b *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. the voltage of vaux may rise up to 2 v. the current i vaux may not exceed 100 a. vs2 i idle_vs2 or i rx_vs2 or i startup_pll_vs2 or i tx_vs2
80 4689f?rke?08/06 ata5811/ata5812 10.11 supply current rx mode clk enabled v vsout enabled 17, 22, 27 i s_rx i s_rx = i rx_vs2 + i vsint + i ext 10.12 current during t startup_pll on pin vs2 i vsout = 0 17 i startup_pll_vs2 9.1 12 ma c 10.13 current in rx polling mode on on pin vs2 10.14 supply current rx polling mode clk enabled v vsout enabled clk disabled v vsout enabled v vsout disabled 17, 22, 27 i s_poll i s_poll = i p + i vsint + i ext i s_poll = i p + i ext i s_poll = i p 10.15 current in tx mode on pin vs2 i vsout = 0 p out = 5 dbm/10 dbm 315 mhz/5 dbm 315 mhz/10 dbm 433.92 mhz/5 dbm 433.92 mhz/10 dbm 868.3 mhz/5 dbm 868.3 mhz/10 dbm 17, 19 i tx_vs2 10.7 16.2 10.9 16.3 11.6 17.8 13.9 21.0 14.0 21.0 15.0 23.0 ma b 10.16 supply current tx mode clk enabled v vsout enabled clk disabled v vsout enabled 17, 22, 27 i s_tx i s_tx = i tx_vs2 + i vsint + i ext i s_tx = i tx_vs2 + i ext 16. electrical characteristics: 2- battery application (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs2 = 4.4v to 6.6v typical values at v vs2 = 6v and t amb = 25c. application according to figure 4-1 on page 8 . f rf = 315.0 mhz/433.92 mhz/868.3 mhz unless otherwise specified no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. the voltage of vaux may rise up to 2 v. the current i vaux may not exceed 100 a. i p i idle_vs2 t sleep i startup_pll_vs2 t startup_pll i rx_vs2 t startup_sig_proc t bitcheck + () + + t sleep t startup_pll t startup_sig_proc t bitcheck ++ + ------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------- =
81 4689f?rke?08/06 ata5811/ata5812 17. electrical characteri stics: car application all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs2 = 4.75v to 5.25v. typical values at v vs2 = 5v and t amb = 25c. application according to figure 3-1 on page 7 . f rf = 315.0 mhz/433.92 mhz/868.3 mh z unless otherwise specified no. parameters test conditions pi n symbol min. typ. max. unit type* 11 car application 11.1 supported voltage range car application 17, 19, 27 v vs2 , v aux 4.75 5.25 v a 11.2 power supply output voltage car application v vs2 = v vaux i vsout 13.5 ma (3.25v regulator mode, v_reg2, see figure 7-1 on page 27 ) 22 v vsout 3.0 3.5 v a 11.3 supply voltage for microcontroller- interface 27 v vsint 2.4 5.25 v a 11.4 threshold hysteresis v thres_2 ? v thres_1 22 ? v thres 60 80 100 mv b 11.5 reset threshold voltage at pin vsout (n_reset) 22 v thres_1 2.18 2.3 2.42 v a 11.6 reset threshold voltage at pin vsout (low_batt) 22 v thres_2 2.26 2.38 2.5 v a 11.7 current in idle mode on pin vs2 and vaux i vsout = 0 clk enabled v vsout enabled clk disabled v vsout enabled v vsout disabled 17, 19 i idle_vs2_vaux 444 380 310 580 500 400 a a a b b b 11.8 supply current in idle mode 17, 19, 22, 27 i s_idle i s_idle = i idle_vs2_vaux + i vsint + i ext 11.9 current in rx mode on pin vs2 and vaux i vsout = 0 17, 19 i rx_vs2_vaux 10.8 14.5 ma b 11.10 supply current in rx mode clk enabled v vsout enabled 17, 19, 22, 27 i s_rx i s_rx = i rx_vs2_vaux + i vsint + i ext *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter vaux vs2 i idle_vs2,vaux or i rx_vs2,vaux or i startup_pll_vs2,vaux or i tx_vs2,vaux
82 4689f?rke?08/06 ata5811/ata5812 11.11 current during t startup_pll on pin vs2 and vaux i vsout = 0 17, 19 i startup_pll_vs2_ vaux 9.1 12 ma c 11.12 current in rx_polling_mode on pin vs2 and vaux 11.13 supply current in rx polling mode clk enabled v vsout enabled clk disabled v vsout enabled v vsout disabled 17, 19, 22, 27 i s_poll i s_poll = i p + i vsint + i ext i s_poll = i p + i ext i s_poll = i p 11.14 current in tx mode on pin vs2 and vaux i vsout = 0 p out = 5dbm/10dbm 315 mhz/5dbm 315 mhz/10dbm 433.92 mhz/5dbm 433.92 mhz/10dbm 868.3 mhz/10dbm 17, 19 i tx_vs2_vaux 10.7 16.2 10.9 16.3 11.6 17.8 13.9 21.0 14.0 21.0 15.0 23.0 ma b 11.15 supply current in tx mode clk enabled v vsout enabled clk disabled v vsout enabled 17, 19, 22, 27 i s_tx i s_tx = i tx_vs2_vaux + i vsint + i ext i s_tx = i tx_vs2_vaux + i ext 17. electrical characteristics: car application (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs2 = 4.75v to 5.25v. typical values at v vs2 = 5v and t amb = 25c. application according to figure 3-1 on page 7 . f rf = 315.0 mhz/433.92 mhz/868.3 mh z unless otherwise specified no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter i p i idle_vs2,vaux t sleep i startup_pll_vs2,vaux t startup_pll i rx_vs2,vaux t startup_sig_proc t bitcheck + () + + t sleep t startup_pll t startup_sig_proc t bitcheck ++ + ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------- --------------------------- =
83 4689f?rke?08/06 ata5811/ata5812 18. digital timing characteristics all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v s2 = 2.4v to 3.6v (1-battery application), v vs2 =4.4v to 6.6v (2-battery application) and v vs2 = 4.75v to 5.25v (car applicat ion), typical values at v vs1 =v vs2 = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* 12 basic clock cycle of the digital circuitry 12.1 basic clock cycle t dclk 16/f xto 16/f xto s a 12.2 extended basic clock cycle xlim = 0 br_range_0 br_range_1 br_range_2 br_range_3 xlim = 1 br_range_0 br_range_1 br_range_2 br_range_3 t xdclk 8 4 2 1 t dclk 16 8 4 2 t dclk 8 4 2 1 t dclk 16 8 4 2 t dclk s a 13 rx mode/rx polling mode 13.1 sleep time sleep and xsleep are defined in control register 4 t sleep sleep x sleep 1024 t dclk sleep x sleep 1024 t dclk ms a 13.2 start-up pll rx mode from idle mode t startup_pll 798.5 t dclk 798.5 t dclk s a 13.3 start-up signal processing br_range_0 br_range_1 br_range_2 br_range_3 t startup_sig_proc 882 498 306 210 t dclk 882 498 306 210 t dclk a 13.4 time for bit-check average time during polling. no rf signal applied. f signal = 1/(2 t ee ) signal data rate manchester (lim_min and lim_max up to 50% of t ee , see figure 11-4 on page 53 ) bit-check time for a valid input signal f sig n bit-check = 0 n bit-check = 3 n bit-check = 6 n bit-check = 9 t bit_check 3/f sig 6/f sig 9/f sig 1/f signal 3.5/f sig 6.5/f sig 9.5/f sig ms c *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
84 4689f?rke?08/06 ata5811/ata5812 13.5 bit-rate range br_range = br_range0 br_range1 br_range2 br_range3 br_range 1.0 2.0 4.0 8.0 2.5 5.0 10.0 20.0 kbit/s a 13.6 minimum time period between edges at pin sdo_tmdo in rx transparent mode xlim = 0 br_range_0 br_range_1 br_range_2 br_range_3 xlim = 1 br_range_0 br_range_1 br_range_2 br_range_3 31 t data_min 10 t xdclk s a 13.7 edge-to-edge time period of the data signal for full sensitivity in rx mode br_range_0 br_range_1 br_range_2 br_range_3 t data 200 100 50 25 500 250 125 62.5 s b 14 tx mode 14.1 start-up time from idle mode t startup 331.5 t dclk 331.5 t dclk s a 15 configuration of the transceiver with 4-wire serial interface 15.1 cs set-up time to rising edge of sck 33, 35 t cs_setup 1.5 t dclk s a 15.2 sck cycle time 33 t cycle 2sa 15.3 sdi_tmdi set-up time to rising edge of sck 32, 33 t setup 250 ns c 15.4 sdi_tmdi hold time from rising edge of sck 32, 33 t hold 250 ns c 15.5 sdo_tmdo enable time from rising edge of cs 31, 35 t out_enable 250 ns c 15.6 sdo_tmdo output delay from falling edge of sck c l = 10 pf 31, 35 t out_delay 250 ns c 15.7 sdo_tmdo disable time from falling edge of cs 31, 33 t out_disable 250 ns c 15.8 cs disable time period 35 t cs_disable 1.5 t dclk s a 15.9 time period sck low to cs high 33, 35 t sck_setup1 250 ns c 18. digital timing char acteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v s2 = 2.4v to 3.6v (1-battery application), v vs2 =4.4v to 6.6v (2-battery application) and v vs2 = 4.75v to 5.25v (car applicat ion), typical values at v vs1 =v vs2 = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
85 4689f?rke?08/06 ata5811/ata5812 15.10 time period sck low to cs low 33, 35 t sck_setup2 250 ns c 15.11 time period cs low to sck high 33, 35 t sck_hold 250 ns c 16 start time push button tn and pwr_on timing of wake-up via pwr_on or tn 16.1 pwr_on high to positive edge on pin irq (see figure 9-4 on page 43 ) from off mode to idle mode, applications according to figure 2-1 on page 6 , figure 3-1 on page 7 and figure 4-1 on page 8 xtal: c m = 4..7 ff (typ. 5 ff) c 0 < 2.2 pf (typ. 1.8 pf) r m 120 ? (typ. 15 ? ) 1-battery application c 1 = c 2 = 68 nf c 3 = c 4 = 68 nf c 5 = 10 nf 2-battery application c 1 = c 4 = 68 nf c 2 = c 3 = 2.2 f c 5 = 10 nf car application c 1 = c 3 = c 4 = 68 nf c 2 = c 12 = 2.2 f c 5 = 10nf 29, 40 t pwr_on_irq_1 0.3 0.45 0.45 0.8 1.3 1.3 ms b 18. digital timing char acteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v s2 = 2.4v to 3.6v (1-battery application), v vs2 =4.4v to 6.6v (2-battery application) and v vs2 = 4.75v to 5.25v (car applicat ion), typical values at v vs1 =v vs2 = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
86 4689f?rke?08/06 ata5811/ata5812 16.2 pwr_on high to positive edge on pin irq (see figure 9-4 on page 43 ) every mode except off mode 29, 40 t pwr_on_irq_2 2 t dclk s a 16.3 tn low to positive edge on pin irq (see figure 9-2 on page 41 ) from off mode to idle mode, applications according to figure 2-1 on page 6 , figure 3-1 on page 7 and figure 4-1 on page 8 xtal: c m = 4..7 ff (typ 5 ff) c 0 < 2.2 pf (typ 1.8 pf) r m 120 ? (typ 15 ? ) 1-battery application c 1 = c 2 = 68 nf c 3 = c 4 = 68 nf c 5 = 10 nf 2-battery application c 1 = c 4 = 68 nf c 2 = c 3 = 2.2 f c 5 = 10 nf car application c 1 = c 3 = c 4 = 68 nf c 2 = c 12 = 2.2 f c 5 = 10 nf 29, 41, 42, 43, 44, 45 t tn_irq 0.3 0.45 0.45 0.8 1.3 1.3 ms b 16.4 push button debounce time every mode except off mode 29, 41, 42, 43, 44, 45 t debounce 8195 t dclk 8195 t dclk s a 18. digital timing char acteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v s2 = 2.4v to 3.6v (1-battery application), v vs2 =4.4v to 6.6v (2-battery application) and v vs2 = 4.75v to 5.25v (car applicat ion), typical values at v vs1 =v vs2 = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
87 4689f?rke?08/06 ata5811/ata5812 19. digital port characteristics all parameter refer to gnd and valid for t amb = ?40c to +105c, v vs1 = v s2 = 2.4v to 3.6v (1 battery application) and v vs2 =4.4v to 6.6v (2 battery application) and v vs2 = 4.75v to 5.25v (car application) typical values at v vs1 =v vs2 = 3v and t amb = 25c unless otherwise specified no. parameters test conditions pi n symbol min. typ. max. unit type* 17 digital ports 17.1 cs input -low level input voltage v vsint = 2.4v to 5.25v 35 v il 0.2 v vsint va -high level input voltage v vsint = 2.4v to 5.25v 35 v ih 0.8 v vsint v vsint va 17.2 sck input -low level input voltage v vsint = 2.4v to 5.25v 33 v il 0.2 v vsint va -high level input voltage v vsint = 2.4v to 5.25v 33 v ih 0.8 v vsint v vsint va 17.3 sdi_tmdi input -low level input voltage v vsint = 2.4v to 5.25v 32 v il 0.2 v vsint va -high level input voltage v vsint = 2.4v to 5.25v 32 v ih 0.8 v vsint v vsint va 17.4 test1 input test1 input must always be directly connected to gnd 20 d 17.5 test2 input test2 input must always be direct connected to gnd 23 d 17.6 pwr_on input -low level input voltage internal pull-down with series connection of 40 k ? 20% resistor and diode 40 v il 0.4 v a -high level input voltage (1) internal pull-down with series connection of 40 k ? 20% resistor and diode 40 v ih 0.8 v vs2 va 17.7 tn input -low level input voltage internal pull-up resistor of 50 k ? 20% 41, 42, 43, 44, 45 v il 0.2 v vs2 va -high level input voltage (1) internal pull-up resistor of 50 k ? 20% 41, 42, 43, 44, 45 v ih v vs2 ?0.5v va 17.8 433_n868 input -low level input voltage 6v il 0.25 v a -input current low 6 i il ?5 a a -high level input voltage 6 v ih 1.7 avcc v a -input current high 6 i ih 1aa *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. if a logic high level is applied to this pin a minimum serial impedance of 100 ? must be ensured for proper operation over full temperature range.
88 4689f?rke?08/06 ata5811/ata5812 17.9 pwr_h input -low level input voltage 9v il 0.25 v a -input current low 9 i il ?5 a a -high level input voltage 9 v ih 1.7 avcc v a -input current high 9 i ih 1aa 17.10 sdo_tmdo output -saturation voltage low v vsint = 2.4v to 5.25v i sdo_tmdo = 250 a 31 v ol 0.15 0.4 v b saturation voltage high v vsint = 2.4v to 5.25v i sdo_tmdo = ?250 a 31 v oh v vsint ? 0.4 v vsint ? 0.15 vb 17.11 irq output -saturation voltage low v vsint = 2.4v to 5.25v i irq = 250 a 29 v ol 0.15 0.4 v b saturation voltage high v vsint = 2.4v to 5.25v i irq = ?250 a 29 v oh v vsint ? 0.4 v vsint ? 0.15 vb 17.12 clk output -saturation voltage low v vsint = 2.4v to 5.25v i clk = 100 a internal series resistor of 1 k ? for spurious reduction in pll 30 v ol 0.15 0.4 v b saturation voltage high v vsint = 2.4v to 5.25v i clk = ?100 a internal series resistor of 1 k ? for spurious reduction in pll 30 v oh v vsint ? 0.4 v vsint ? 0.15 vb 17.13 n_reset output -saturation voltage low v vsint = 2.4v to 5.25v i n_reset = 250 a 28 v ol 0.15 0.4 v b -saturation voltage high v vsint = 2.4v to 5.25v i n_reset = ?250 a 28 v oh v vsint ? 0.4 v vsint ? 0.15 vb 17.14 rx_active output -saturation voltage high v vsint = 2.4v to 5.25v i rx_active = ?1.5 ma 46 v oh v avcc ?0.5v v avcc ?0.15v vb -saturation voltage low v vsint = 2.4v to 5.25v i rx_active = 25 a 46 v ol 0.25 0.4 v b 17.15 dem_out output saturation voltage low open drain output i dem_out = 250 a 34 v ol 0.15 0.4 v b 19. digital port characteristics (continued) all parameter refer to gnd and valid for t amb = ?40c to +105c, v vs1 = v s2 = 2.4v to 3.6v (1 battery application) and v vs2 =4.4v to 6.6v (2 battery application) and v vs2 = 4.75v to 5.25v (car application) typical values at v vs1 =v vs2 = 3v and t amb = 25c unless otherwise specified no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. if a logic high level is applied to this pin a minimum serial impedance of 100 ? must be ensured for proper operation over full temperature range.
89 4689f?rke?08/06 ata5811/ata5812 21. package information 20. ordering information extended type number package remarks ATA5811-PLQW qfn48 7 mm 7 mm, pb-free ata5812-plqw qfn48 7 mm 7 mm, pb-free 0.4 0.1 7 5.5 5.1 0.5 nom. 48 12 1 48 37 13 24 25 36 12 1 specifications according to din technical drawings issue: 1; 14.01.03 drawing-no.: 6.543-5089.02-4 package: qfn 48 - 7 x 7 exposed pad 5.1 x 5.1 dimensions in mm not indicated tolerances 0.05 0.23 0.05 -0.05 1 max. +0
90 4689f?rke?08/06 ata5811/ata5812 22. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4689f-rke-08/06 ? quality of drawings improved 4689e-rke-06/06 ? put datasheet in a new template ? kbaud replaced through kbit/s ? baud replaced through bit ? table 11-6 ?interrupt handling? on page 62 changed 4689d-rke-09/05 ? pb-free logo on page 1 added ? table 1-1 ?pin description? on pages 4 to 5 changed ? ordering information on page 89 changed
91 4689f?rke?08/06 ata5811/ata5812 23. table of contents features ................ ................ .............. ............... .............. .............. ............ 1 applications ......... ................ .............. ............... .............. .............. ............ 2 benefits................... .............. .............. ............... .............. .............. ............ 2 1 general description ............ .............. ............... .............. .............. ............ 2 2 typical key fob or sensor a pplication with 1 battery ............. ............ 6 3 typical car or sensor base-s tation application ...... ................. ............ 7 4 typical key fob application, 2 batteries ................. ................. ............ 8 5 rf transceiver ........... ................ ................. ................ ................. ............ 9 6 xto ................ ................ ................. ................ ................. .............. .......... 23 7 power supply ........... ................ ................ ................. ................ ............. 27 8 microcontroller interface .... .............. ............... .............. .............. .......... 33 9 digital control logic ........... .............. ............... .............. .............. .......... 33 10 transceiver configuration .... .............. .............. .............. .............. ........ 46 11 operation modes ............... ................ ............... .............. .............. .......... 49 12 absolute maximum ratings .... ................ ................. ................ ............. 63 13 thermal resistance ............ .............. ............... .............. .............. .......... 63 14 electrical characteristics: general ........ ................. ................ ............. 63 15 electrical characteristic: 1-battery appl ication .............. ............ ........ 76 16 electrical characteristics: 2-battery app lication ............ ............ ........ 79 17 electrical characteristics: car application ... .............. .............. .......... 81 18 digital timing characteristi cs .............. .............. .............. ............ ........ 83 19 digital port characteristics .............. ............... .............. .............. .......... 87 20 ordering information .......... .............. ............... .............. .............. .......... 89 21 package information .......... .............. ............... .............. .............. .......... 89 22 revision history ....... ................ ................ ................. ................ ............. 90
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